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Fix cmp emission on msp430: we definitely should turn stuff like
"icmp lhs, rhs" into "cmp rhs, lhs". This should fix PR5979. llvm-svn: 93496
1 parent 89880c8 commit cefa7ad

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2 files changed

+27
-25
lines changed

2 files changed

+27
-25
lines changed

llvm/lib/Target/MSP430/MSP430ISelLowering.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -660,16 +660,16 @@ static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
660660
default: llvm_unreachable("Invalid integer condition!");
661661
case ISD::SETEQ:
662662
TCC = MSP430CC::COND_E; // aka COND_Z
663-
// Minor optimization: if RHS is a constant, swap operands, then the
663+
// Minor optimization: if LHS is a constant, swap operands, then the
664664
// constant can be folded into comparison.
665-
if (RHS.getOpcode() == ISD::Constant)
665+
if (LHS.getOpcode() == ISD::Constant)
666666
std::swap(LHS, RHS);
667667
break;
668668
case ISD::SETNE:
669669
TCC = MSP430CC::COND_NE; // aka COND_NZ
670-
// Minor optimization: if RHS is a constant, swap operands, then the
670+
// Minor optimization: if LHS is a constant, swap operands, then the
671671
// constant can be folded into comparison.
672-
if (RHS.getOpcode() == ISD::Constant)
672+
if (LHS.getOpcode() == ISD::Constant)
673673
std::swap(LHS, RHS);
674674
break;
675675
case ISD::SETULE:
@@ -1014,8 +1014,8 @@ MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI,
10141014
// BB:
10151015
// cmp 0, N
10161016
// je RemBB
1017-
BuildMI(BB, dl, TII.get(MSP430::CMP8ir))
1018-
.addImm(0).addReg(ShiftAmtSrcReg);
1017+
BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1018+
.addReg(ShiftAmtSrcReg).addImm(0);
10191019
BuildMI(BB, dl, TII.get(MSP430::JCC))
10201020
.addMBB(RemBB)
10211021
.addImm(MSP430CC::COND_E);

llvm/lib/Target/MSP430/MSP430InstrInfo.td

Lines changed: 21 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -819,38 +819,40 @@ def SWPB16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
819819
// Integer comparisons
820820
let Defs = [SRW] in {
821821
def CMP8rr : Pseudo<(outs), (ins GR8:$src1, GR8:$src2),
822-
"cmp.b\t{$src1, $src2}",
822+
"cmp.b\t{$src2, $src1}",
823823
[(MSP430cmp GR8:$src1, GR8:$src2), (implicit SRW)]>;
824824
def CMP16rr : Pseudo<(outs), (ins GR16:$src1, GR16:$src2),
825-
"cmp.w\t{$src1, $src2}",
825+
"cmp.w\t{$src2, $src1}",
826826
[(MSP430cmp GR16:$src1, GR16:$src2), (implicit SRW)]>;
827827

828-
def CMP8ir : Pseudo<(outs), (ins i8imm:$src1, GR8:$src2),
829-
"cmp.b\t{$src1, $src2}",
830-
[(MSP430cmp imm:$src1, GR8:$src2), (implicit SRW)]>;
831-
def CMP16ir : Pseudo<(outs), (ins i16imm:$src1, GR16:$src2),
832-
"cmp.w\t{$src1, $src2}",
833-
[(MSP430cmp imm:$src1, GR16:$src2), (implicit SRW)]>;
834-
835-
def CMP8im : Pseudo<(outs), (ins i8imm:$src1, memsrc:$src2),
836-
"cmp.b\t{$src1, $src2}",
837-
[(MSP430cmp (i8 imm:$src1), (load addr:$src2)), (implicit SRW)]>;
838-
def CMP16im : Pseudo<(outs), (ins i16imm:$src1, memsrc:$src2),
839-
"cmp.w\t{$src1, $src2}",
840-
[(MSP430cmp (i16 imm:$src1), (load addr:$src2)), (implicit SRW)]>;
828+
def CMP8ri : Pseudo<(outs), (ins GR8:$src1, i8imm:$src2),
829+
"cmp.b\t{$src2, $src1}",
830+
[(MSP430cmp GR8:$src1, imm:$src2), (implicit SRW)]>;
831+
def CMP16ri : Pseudo<(outs), (ins GR16:$src1, i16imm:$src2),
832+
"cmp.w\t{$src2, $src1}",
833+
[(MSP430cmp GR16:$src1, imm:$src2), (implicit SRW)]>;
834+
835+
def CMP8mi : Pseudo<(outs), (ins memsrc:$src1, i8imm:$src2),
836+
"cmp.b\t{$src2, $src1}",
837+
[(MSP430cmp (load addr:$src1),
838+
(i8 imm:$src2)), (implicit SRW)]>;
839+
def CMP16mi : Pseudo<(outs), (ins memsrc:$src1, i16imm:$src2),
840+
"cmp.w\t{$src2, $src1}",
841+
[(MSP430cmp (load addr:$src1),
842+
(i16 imm:$src2)), (implicit SRW)]>;
841843

842844
def CMP8rm : Pseudo<(outs), (ins GR8:$src1, memsrc:$src2),
843-
"cmp.b\t{$src1, $src2}",
845+
"cmp.b\t{$src2, $src1}",
844846
[(MSP430cmp GR8:$src1, (load addr:$src2)), (implicit SRW)]>;
845847
def CMP16rm : Pseudo<(outs), (ins GR16:$src1, memsrc:$src2),
846-
"cmp.w\t{$src1, $src2}",
848+
"cmp.w\t{$src2, $src1}",
847849
[(MSP430cmp GR16:$src1, (load addr:$src2)), (implicit SRW)]>;
848850

849851
def CMP8mr : Pseudo<(outs), (ins memsrc:$src1, GR8:$src2),
850-
"cmp.b\t{$src1, $src2}",
852+
"cmp.b\t{$src2, $src1}",
851853
[(MSP430cmp (load addr:$src1), GR8:$src2), (implicit SRW)]>;
852854
def CMP16mr : Pseudo<(outs), (ins memsrc:$src1, GR16:$src2),
853-
"cmp.w\t{$src1, $src2}",
855+
"cmp.w\t{$src2, $src1}",
854856
[(MSP430cmp (load addr:$src1), GR16:$src2), (implicit SRW)]>;
855857

856858

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