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[DAG] visitSIGN_EXTEND_INREG - avoid SDLoc duplication. NFC.
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‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 28 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -14812,14 +14812,15 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
1481214812
EVT ExtVT = cast<VTSDNode>(N1)->getVT();
1481314813
unsigned VTBits = VT.getScalarSizeInBits();
1481414814
unsigned ExtVTBits = ExtVT.getScalarSizeInBits();
14815+
SDLoc DL(N);
1481514816

1481614817
// sext_vector_inreg(undef) = 0 because the top bit will all be the same.
1481714818
if (N0.isUndef())
14818-
return DAG.getConstant(0, SDLoc(N), VT);
14819+
return DAG.getConstant(0, DL, VT);
1481914820

1482014821
// fold (sext_in_reg c1) -> c1
1482114822
if (DAG.isConstantIntBuildVectorOrConstantInt(N0))
14822-
return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, N0, N1);
14823+
return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, N0, N1);
1482314824

1482414825
// If the input is already sign extended, just drop the extension.
1482514826
if (ExtVTBits >= DAG.ComputeMaxSignificantBits(N0))
@@ -14828,8 +14829,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
1482814829
// fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
1482914830
if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1483014831
ExtVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT()))
14831-
return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, N0.getOperand(0),
14832-
N1);
14832+
return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, N0.getOperand(0), N1);
1483314833

1483414834
// fold (sext_in_reg (sext x)) -> (sext x)
1483514835
// fold (sext_in_reg (aext x)) -> (sext x)
@@ -14841,7 +14841,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
1484114841
if ((N00Bits <= ExtVTBits ||
1484214842
DAG.ComputeMaxSignificantBits(N00) <= ExtVTBits) &&
1484314843
(!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
14844-
return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N00);
14844+
return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, N00);
1484514845
}
1484614846

1484714847
// fold (sext_in_reg (*_extend_vector_inreg x)) -> (sext_vector_inreg x)
@@ -14859,7 +14859,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
1485914859
DAG.ComputeMaxSignificantBits(N00) <= ExtVTBits))) &&
1486014860
(!LegalOperations ||
1486114861
TLI.isOperationLegal(ISD::SIGN_EXTEND_VECTOR_INREG, VT)))
14862-
return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, SDLoc(N), VT, N00);
14862+
return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, VT, N00);
1486314863
}
1486414864

1486514865
// fold (sext_in_reg (zext x)) -> (sext x)
@@ -14868,12 +14868,12 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
1486814868
SDValue N00 = N0.getOperand(0);
1486914869
if (N00.getScalarValueSizeInBits() == ExtVTBits &&
1487014870
(!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
14871-
return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N00);
14871+
return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, N00);
1487214872
}
1487314873

1487414874
// fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
1487514875
if (DAG.MaskedValueIsZero(N0, APInt::getOneBitSet(VTBits, ExtVTBits - 1)))
14876-
return DAG.getZeroExtendInReg(N0, SDLoc(N), ExtVT);
14876+
return DAG.getZeroExtendInReg(N0, DL, ExtVT);
1487714877

1487814878
// fold operands of sext_in_reg based on knowledge that the top bits are not
1487914879
// demanded.
@@ -14895,7 +14895,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
1489514895
// extended enough.
1489614896
unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
1489714897
if (((VTBits - ExtVTBits) - ShAmt->getZExtValue()) < InSignBits)
14898-
return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0.getOperand(0),
14898+
return DAG.getNode(ISD::SRA, DL, VT, N0.getOperand(0),
1489914899
N0.getOperand(1));
1490014900
}
1490114901
}
@@ -14904,37 +14904,33 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
1490414904
// If sextload is not supported by target, we can only do the combine when
1490514905
// load has one use. Doing otherwise can block folding the extload with other
1490614906
// extends that the target does support.
14907-
if (ISD::isEXTLoad(N0.getNode()) &&
14908-
ISD::isUNINDEXEDLoad(N0.getNode()) &&
14907+
if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
1490914908
ExtVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
1491014909
((!LegalOperations && cast<LoadSDNode>(N0)->isSimple() &&
1491114910
N0.hasOneUse()) ||
1491214911
TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, ExtVT))) {
14913-
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
14914-
SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
14915-
LN0->getChain(),
14916-
LN0->getBasePtr(), ExtVT,
14917-
LN0->getMemOperand());
14912+
auto *LN0 = cast<LoadSDNode>(N0);
14913+
SDValue ExtLoad =
14914+
DAG.getExtLoad(ISD::SEXTLOAD, DL, VT, LN0->getChain(),
14915+
LN0->getBasePtr(), ExtVT, LN0->getMemOperand());
1491814916
CombineTo(N, ExtLoad);
1491914917
CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
1492014918
AddToWorklist(ExtLoad.getNode());
14921-
return SDValue(N, 0); // Return N so it doesn't get rechecked!
14919+
return SDValue(N, 0); // Return N so it doesn't get rechecked!
1492214920
}
1492314921

1492414922
// fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
1492514923
if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
14926-
N0.hasOneUse() &&
14927-
ExtVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
14924+
N0.hasOneUse() && ExtVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
1492814925
((!LegalOperations && cast<LoadSDNode>(N0)->isSimple()) &&
1492914926
TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, ExtVT))) {
14930-
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
14931-
SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
14932-
LN0->getChain(),
14933-
LN0->getBasePtr(), ExtVT,
14934-
LN0->getMemOperand());
14927+
auto *LN0 = cast<LoadSDNode>(N0);
14928+
SDValue ExtLoad =
14929+
DAG.getExtLoad(ISD::SEXTLOAD, DL, VT, LN0->getChain(),
14930+
LN0->getBasePtr(), ExtVT, LN0->getMemOperand());
1493514931
CombineTo(N, ExtLoad);
1493614932
CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
14937-
return SDValue(N, 0); // Return N so it doesn't get rechecked!
14933+
return SDValue(N, 0); // Return N so it doesn't get rechecked!
1493814934
}
1493914935

1494014936
// fold (sext_inreg (masked_load x)) -> (sext_masked_load x)
@@ -14944,7 +14940,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
1494414940
Ld->getExtensionType() != ISD::LoadExtType::NON_EXTLOAD &&
1494514941
TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, ExtVT)) {
1494614942
SDValue ExtMaskedLoad = DAG.getMaskedLoad(
14947-
VT, SDLoc(N), Ld->getChain(), Ld->getBasePtr(), Ld->getOffset(),
14943+
VT, DL, Ld->getChain(), Ld->getBasePtr(), Ld->getOffset(),
1494814944
Ld->getMask(), Ld->getPassThru(), ExtVT, Ld->getMemOperand(),
1494914945
Ld->getAddressingMode(), ISD::SEXTLOAD, Ld->isExpandingLoad());
1495014946
CombineTo(N, ExtMaskedLoad);
@@ -14955,15 +14951,14 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
1495514951

1495614952
// fold (sext_inreg (masked_gather x)) -> (sext_masked_gather x)
1495714953
if (auto *GN0 = dyn_cast<MaskedGatherSDNode>(N0)) {
14958-
if (SDValue(GN0, 0).hasOneUse() &&
14959-
ExtVT == GN0->getMemoryVT() &&
14954+
if (SDValue(GN0, 0).hasOneUse() && ExtVT == GN0->getMemoryVT() &&
1496014955
TLI.isVectorLoadExtDesirable(SDValue(SDValue(GN0, 0)))) {
1496114956
SDValue Ops[] = {GN0->getChain(), GN0->getPassThru(), GN0->getMask(),
1496214957
GN0->getBasePtr(), GN0->getIndex(), GN0->getScale()};
1496314958

1496414959
SDValue ExtLoad = DAG.getMaskedGather(
14965-
DAG.getVTList(VT, MVT::Other), ExtVT, SDLoc(N), Ops,
14966-
GN0->getMemOperand(), GN0->getIndexType(), ISD::SEXTLOAD);
14960+
DAG.getVTList(VT, MVT::Other), ExtVT, DL, Ops, GN0->getMemOperand(),
14961+
GN0->getIndexType(), ISD::SEXTLOAD);
1496714962

1496814963
CombineTo(N, ExtLoad);
1496914964
CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
@@ -14976,7 +14971,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
1497614971
if (ExtVTBits <= 16 && N0.getOpcode() == ISD::OR) {
1497714972
if (SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
1497814973
N0.getOperand(1), false))
14979-
return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, BSwap, N1);
14974+
return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, BSwap, N1);
1498014975
}
1498114976

1498214977
// Fold (iM_signext_inreg
@@ -14993,8 +14988,8 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
1499314988
(!LegalOperations ||
1499414989
TLI.isOperationLegal(ISD::SIGN_EXTEND, InnerExtVT))) {
1499514990
SDValue SignExtExtendee =
14996-
DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), InnerExtVT, Extendee);
14997-
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), VT, SignExtExtendee,
14991+
DAG.getNode(ISD::SIGN_EXTEND, DL, InnerExtVT, Extendee);
14992+
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SignExtExtendee,
1499814993
N0.getOperand(1));
1499914994
}
1500014995
}

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