[SPARC][IAS] Add definitions for UA 2007 instructions

koachan · web-flow · commit cf19c6b5e237 · 2025-05-12T13:26:56.000+07:00
Reviewers: rorth, s-barannikov, brad0 Reviewed By: s-barannikov Pull Request: #138401
diff --git a/llvm/lib/Target/Sparc/Sparc.td b/llvm/lib/Target/Sparc/Sparc.td
@@ -52,6 +52,9 @@ def FeatureVIS3
 def FeatureUA2005
   : SubtargetFeature<"ua2005", "IsUA2005", "true",
                      "Enable UltraSPARC Architecture 2005 extensions">;
+def FeatureUA2007
+  : SubtargetFeature<"ua2007", "IsUA2007", "true",
+                     "Enable UltraSPARC Architecture 2007 extensions">;
 def FeatureLeon
   : SubtargetFeature<"leon", "IsLeon", "true",
                      "Enable LEON extensions">;
@@ -160,10 +163,10 @@ def : Proc<"niagara2",        [FeatureV9, FeatureV8Deprecated, UsePopc,
                                FeatureVIS, FeatureVIS2, FeatureUA2005]>;
 def : Proc<"niagara3",        [FeatureV9, FeatureV8Deprecated, UsePopc,
                                FeatureVIS, FeatureVIS2, FeatureVIS3,
-                               FeatureUA2005]>;
+                               FeatureUA2005, FeatureUA2007]>;
 def : Proc<"niagara4",        [FeatureV9, FeatureV8Deprecated, UsePopc,
                                FeatureVIS, FeatureVIS2, FeatureVIS3,
-                               FeatureUA2005]>;
+                               FeatureUA2005, FeatureUA2007]>;
 
 // LEON 2 FT generic
 def : Processor<"leon2", LEON2Itineraries,
diff --git a/llvm/lib/Target/Sparc/SparcInstrFormats.td b/llvm/lib/Target/Sparc/SparcInstrFormats.td
@@ -260,6 +260,23 @@ multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
                  itin>;
 }
 
+// 4-operand instructions.
+class F3_4<bits<6> op3val, bits<4> op5val, dag outs, dag ins,
+           string asmstr, list<dag> pattern = [], InstrItinClass itin = NoItinerary>
+   : F3<outs, ins, asmstr, pattern, itin> {
+  bits<4> op5;
+  bits<5> rs3;
+  bits<5> rs2;
+
+  let op         = 2;
+  let op3        = op3val;
+  let op5        = op5val;
+
+  let Inst{13-9} = rs3;
+  let Inst{8-5}  = op5;
+  let Inst{4-0}  = rs2;
+}
+
 class F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern,
          InstrItinClass itin = NoItinerary>
    : InstSP<outs, ins, asmstr, pattern, itin> {
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td
@@ -51,6 +51,10 @@ def HasVIS3 : Predicate<"Subtarget->isVIS3()">,
 def HasUA2005 : Predicate<"Subtarget->isUA2005()">,
                 AssemblerPredicate<(all_of FeatureUA2005)>;
 
+// HasUA2007 - This is true when the target processor has UA 2007 extensions.
+def HasUA2007 : Predicate<"Subtarget->isUA2007()">,
+                AssemblerPredicate<(all_of FeatureUA2007)>;
+
 // HasHardQuad - This is true when the target processor supports quad floating
 // point instructions.
 def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">;
diff --git a/llvm/lib/Target/Sparc/SparcInstrUAOSA.td b/llvm/lib/Target/Sparc/SparcInstrUAOSA.td
@@ -7,7 +7,7 @@
 //===----------------------------------------------------------------------===//
 //
 // This file contains instruction formats, definitions and patterns needed for
-// UA 2005 instructions on SPARC.
+// UA 2005 and UA 2007 instructions on SPARC.
 //===----------------------------------------------------------------------===//
 
 class UA2005RegWin<string asmstr, bits<5> fcn>
@@ -17,6 +17,12 @@ class UA2005RegWin<string asmstr, bits<5> fcn>
   let rs2 = 0;
 }
 
+// Convenience template for 4-operand instructions
+class FourOp<string OpcStr, bits<6> op3val, bits<4> op5val,
+        RegisterClass RC>
+      : F3_4<op3val, op5val, (outs RC:$rd), (ins RC:$rs1, RC:$rs2, RC:$rs3),
+        !strconcat(OpcStr, " $rs1, $rs2, $rs3, $rd")>;
+
 // UltraSPARC Architecture 2005 Instructions
 let Predicates = [HasUA2005] in {
 let hasSideEffects = 1 in {
@@ -26,3 +32,16 @@ def NORMALW  : UA2005RegWin<"normalw", 0b00100>;
 def OTHERW   : UA2005RegWin<"otherw", 0b00011>;
 }
 } // Predicates = [HasUA2005]
+
+// UltraSPARC Architecture 2007 Instructions
+let Predicates = [HasUA2007] in {
+def FMADDS : FourOp<"fmadds", 0b110111, 0b0001, FPRegs>;
+def FMADDD : FourOp<"fmaddd", 0b110111, 0b0010, DFPRegs>;
+def FMSUBS : FourOp<"fmsubs", 0b110111, 0b0101, FPRegs>;
+def FMSUBD : FourOp<"fmsubd", 0b110111, 0b0110, DFPRegs>;
+
+def FNMADDS : FourOp<"fnmadds", 0b110111, 0b1101, FPRegs>;
+def FNMADDD : FourOp<"fnmaddd", 0b110111, 0b1110, DFPRegs>;
+def FNMSUBS : FourOp<"fnmsubs", 0b110111, 0b1001, FPRegs>;
+def FNMSUBD : FourOp<"fnmsubd", 0b110111, 0b1010, DFPRegs>;
+} // Predicates = [HasUA2007]
diff --git a/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt b/llvm/test/MC/Disassembler/Sparc/sparc-ua-osa.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble %s -triple=sparcv9-unknown-linux -mattr=+ua2005 | FileCheck %s
+# RUN: llvm-mc --disassemble %s -triple=sparcv9-unknown-linux -mattr=+ua2005,+ua2007 | FileCheck %s
 
 ## UA 2005 instructions.
 
@@ -10,3 +10,22 @@
 0x87,0x88,0x00,0x00
 # CHECK: normalw
 0x89,0x88,0x00,0x00
+
+## UA 2007 instructions.
+
+# CHECK: fmadds  %f1, %f3, %f5, %f7
+0x8f,0xb8,0x4a,0x23
+# CHECK: fmaddd  %f0, %f2, %f4, %f6
+0x8d,0xb8,0x08,0x42
+# CHECK: fmsubs  %f1, %f3, %f5, %f7
+0x8f,0xb8,0x4a,0xa3
+# CHECK: fmsubd  %f0, %f2, %f4, %f6
+0x8d,0xb8,0x08,0xc2
+# CHECK: fnmadds  %f1, %f3, %f5, %f7
+0x8f,0xb8,0x4b,0xa3
+# CHECK: fnmaddd  %f0, %f2, %f4, %f6
+0x8d,0xb8,0x09,0xc2
+# CHECK: fnmsubs  %f1, %f3, %f5, %f7
+0x8f,0xb8,0x4b,0x23
+# CHECK: fnmsubd  %f0, %f2, %f4, %f6
+0x8d,0xb8,0x09,0x42
diff --git a/llvm/test/MC/Sparc/sparc-ua2007.s b/llvm/test/MC/Sparc/sparc-ua2007.s
@@ -0,0 +1,30 @@
+! RUN: not llvm-mc %s -triple=sparcv9 -show-encoding 2>&1 | FileCheck %s --check-prefixes=NO-UA2007 --implicit-check-not=error:
+! RUN: llvm-mc %s -triple=sparcv9 -mattr=+ua2007 -show-encoding | FileCheck %s --check-prefixes=UA2007
+
+!! UA 2007 instructions.
+
+! NO-UA2007: error: instruction requires a CPU feature not currently enabled
+! UA2007: fmadds %f1, %f3, %f5, %f7               ! encoding: [0x8f,0xb8,0x4a,0x23]
+fmadds %f1, %f3, %f5, %f7
+! NO-UA2007: error: instruction requires a CPU feature not currently enabled
+! UA2007: fmaddd %f0, %f2, %f4, %f6               ! encoding: [0x8d,0xb8,0x08,0x42]
+fmaddd %f0, %f2, %f4, %f6
+! NO-UA2007: error: instruction requires a CPU feature not currently enabled
+! UA2007: fmsubs %f1, %f3, %f5, %f7               ! encoding: [0x8f,0xb8,0x4a,0xa3]
+fmsubs %f1, %f3, %f5, %f7
+! NO-UA2007: error: instruction requires a CPU feature not currently enabled
+! UA2007: fmsubd %f0, %f2, %f4, %f6               ! encoding: [0x8d,0xb8,0x08,0xc2]
+fmsubd %f0, %f2, %f4, %f6
+
+! NO-UA2007: error: instruction requires a CPU feature not currently enabled
+! UA2007: fnmadds %f1, %f3, %f5, %f7              ! encoding: [0x8f,0xb8,0x4b,0xa3]
+fnmadds %f1, %f3, %f5, %f7
+! NO-UA2007: error: instruction requires a CPU feature not currently enabled
+! UA2007: fnmaddd %f0, %f2, %f4, %f6              ! encoding: [0x8d,0xb8,0x09,0xc2]
+fnmaddd %f0, %f2, %f4, %f6
+! NO-UA2007: error: instruction requires a CPU feature not currently enabled
+! UA2007: fnmsubs %f1, %f3, %f5, %f7              ! encoding: [0x8f,0xb8,0x4b,0x23]
+fnmsubs %f1, %f3, %f5, %f7
+! NO-UA2007: error: instruction requires a CPU feature not currently enabled
+! UA2007: fnmsubd %f0, %f2, %f4, %f6              ! encoding: [0x8d,0xb8,0x09,0x42]
+fnmsubd %f0, %f2, %f4, %f6
