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[RISCV] Minimally modify incoming state in transferBefore (#72352)
transferBefore currently takes an incoming state and an instruction, computes the new state needed for the instruction, and then modifies that new state to be more similar to the incoming state. This patch reverses the approach by instead taking the incoming state and modifying only the bits that are demanded by the instruction.
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llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

Lines changed: 44 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -491,6 +491,8 @@ class VSETVLIInfo {
491491

492492
unsigned getSEW() const { return SEW; }
493493
RISCVII::VLMUL getVLMUL() const { return VLMul; }
494+
bool getTailAgnostic() const { return TailAgnostic; }
495+
bool getMaskAgnostic() const { return MaskAgnostic; }
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495497
bool hasNonZeroAVL(const MachineRegisterInfo &MRI) const {
496498
if (hasAVLImm())
@@ -1040,9 +1042,13 @@ bool RISCVInsertVSETVLI::needVSETVLI(const MachineInstr &MI,
10401042
return true;
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}
10421044

1043-
// Given an incoming state reaching MI, modifies that state so that it is minimally
1044-
// compatible with MI. The resulting state is guaranteed to be semantically legal
1045-
// for MI, but may not be the state requested by MI.
1045+
static VSETVLIInfo adjustIncoming(VSETVLIInfo PrevInfo, VSETVLIInfo NewInfo,
1046+
DemandedFields &Demanded,
1047+
const MachineRegisterInfo *MRI);
1048+
1049+
// Given an incoming state reaching MI, minimally modifies that state so that it
1050+
// is compatible with MI. The resulting state is guaranteed to be semantically
1051+
// legal for MI, but may not be the state requested by MI.
10461052
void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
10471053
const MachineInstr &MI) const {
10481054
uint64_t TSFlags = MI.getDesc().TSFlags;
@@ -1055,20 +1061,47 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
10551061
return;
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10571063
const VSETVLIInfo PrevInfo = Info;
1058-
Info = NewInfo;
1064+
if (Info.hasSEWLMULRatioOnly() || !Info.isValid() || Info.isUnknown())
1065+
Info = NewInfo;
10591066

1060-
if (!RISCVII::hasVLOp(TSFlags))
1067+
if (!RISCVII::hasVLOp(TSFlags)) {
1068+
Info = NewInfo;
10611069
return;
1070+
}
1071+
1072+
DemandedFields Demanded = getDemanded(MI, MRI, ST);
1073+
const VSETVLIInfo IncomingInfo =
1074+
adjustIncoming(PrevInfo, NewInfo, Demanded, MRI);
1075+
1076+
if (Demanded.usedVL())
1077+
Info.setAVL(IncomingInfo);
1078+
1079+
Info.setVTYPE(
1080+
((Demanded.LMUL || Demanded.SEWLMULRatio) ? IncomingInfo : Info)
1081+
.getVLMUL(),
1082+
((Demanded.SEW || Demanded.SEWLMULRatio) ? IncomingInfo : Info).getSEW(),
1083+
// Prefer tail/mask agnostic since it can be relaxed to undisturbed later
1084+
// if needed.
1085+
(Demanded.TailPolicy ? IncomingInfo : Info).getTailAgnostic() ||
1086+
IncomingInfo.getTailAgnostic(),
1087+
(Demanded.MaskPolicy ? IncomingInfo : Info).getMaskAgnostic() ||
1088+
IncomingInfo.getMaskAgnostic());
1089+
}
1090+
1091+
static VSETVLIInfo adjustIncoming(VSETVLIInfo PrevInfo, VSETVLIInfo NewInfo,
1092+
DemandedFields &Demanded,
1093+
const MachineRegisterInfo *MRI) {
1094+
VSETVLIInfo Info = NewInfo;
10621095

10631096
// If we don't use LMUL or the SEW/LMUL ratio, then adjust LMUL so that we
10641097
// maintain the SEW/LMUL ratio. This allows us to eliminate VL toggles in more
10651098
// places.
1066-
DemandedFields Demanded = getDemanded(MI, MRI, ST);
10671099
if (!Demanded.LMUL && !Demanded.SEWLMULRatio && PrevInfo.isValid() &&
10681100
!PrevInfo.isUnknown()) {
10691101
if (auto NewVLMul = RISCVVType::getSameRatioLMUL(
10701102
PrevInfo.getSEW(), PrevInfo.getVLMUL(), Info.getSEW()))
10711103
Info.setVLMul(*NewVLMul);
1104+
Demanded.LMUL = true;
10721105
}
10731106

10741107
// If we only demand VL zeroness (i.e. vmv.s.x and vmv.x.s), then there are
@@ -1080,8 +1113,12 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
10801113
// to prevent extending live range of an avl register operand.
10811114
// TODO: We can probably relax this for immediates.
10821115
if (Demanded.VLZeroness && !Demanded.VLAny && PrevInfo.isValid() &&
1083-
PrevInfo.hasEquallyZeroAVL(Info, *MRI) && Info.hasSameVLMAX(PrevInfo))
1116+
PrevInfo.hasEquallyZeroAVL(Info, *MRI) && Info.hasSameVLMAX(PrevInfo)) {
10841117
Info.setAVL(PrevInfo);
1118+
Demanded.demandVL();
1119+
}
1120+
1121+
return Info;
10851122
}
10861123

10871124
// Given a state with which we evaluated MI (see transferBefore above for why

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