@@ -491,6 +491,8 @@ class VSETVLIInfo {
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unsigned getSEW () const { return SEW; }
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RISCVII::VLMUL getVLMUL () const { return VLMul; }
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+ bool getTailAgnostic () const { return TailAgnostic; }
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+ bool getMaskAgnostic () const { return MaskAgnostic; }
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bool hasNonZeroAVL (const MachineRegisterInfo &MRI) const {
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if (hasAVLImm ())
@@ -1040,9 +1042,13 @@ bool RISCVInsertVSETVLI::needVSETVLI(const MachineInstr &MI,
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return true ;
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}
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- // Given an incoming state reaching MI, modifies that state so that it is minimally
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- // compatible with MI. The resulting state is guaranteed to be semantically legal
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- // for MI, but may not be the state requested by MI.
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+ static VSETVLIInfo adjustIncoming (VSETVLIInfo PrevInfo, VSETVLIInfo NewInfo,
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+ DemandedFields &Demanded,
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+ const MachineRegisterInfo *MRI);
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+
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+ // Given an incoming state reaching MI, minimally modifies that state so that it
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+ // is compatible with MI. The resulting state is guaranteed to be semantically
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+ // legal for MI, but may not be the state requested by MI.
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void RISCVInsertVSETVLI::transferBefore (VSETVLIInfo &Info,
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const MachineInstr &MI) const {
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uint64_t TSFlags = MI.getDesc ().TSFlags ;
@@ -1055,20 +1061,47 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
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return ;
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const VSETVLIInfo PrevInfo = Info;
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- Info = NewInfo;
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+ if (Info.hasSEWLMULRatioOnly () || !Info.isValid () || Info.isUnknown ())
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+ Info = NewInfo;
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- if (!RISCVII::hasVLOp (TSFlags))
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+ if (!RISCVII::hasVLOp (TSFlags)) {
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+ Info = NewInfo;
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return ;
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+ }
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+
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+ DemandedFields Demanded = getDemanded (MI, MRI, ST);
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+ const VSETVLIInfo IncomingInfo =
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+ adjustIncoming (PrevInfo, NewInfo, Demanded, MRI);
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+
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+ if (Demanded.usedVL ())
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+ Info.setAVL (IncomingInfo);
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+
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+ Info.setVTYPE (
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+ ((Demanded.LMUL || Demanded.SEWLMULRatio ) ? IncomingInfo : Info)
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+ .getVLMUL (),
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+ ((Demanded.SEW || Demanded.SEWLMULRatio ) ? IncomingInfo : Info).getSEW (),
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+ // Prefer tail/mask agnostic since it can be relaxed to undisturbed later
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+ // if needed.
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+ (Demanded.TailPolicy ? IncomingInfo : Info).getTailAgnostic () ||
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+ IncomingInfo.getTailAgnostic (),
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+ (Demanded.MaskPolicy ? IncomingInfo : Info).getMaskAgnostic () ||
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+ IncomingInfo.getMaskAgnostic ());
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+ }
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+
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+ static VSETVLIInfo adjustIncoming (VSETVLIInfo PrevInfo, VSETVLIInfo NewInfo,
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+ DemandedFields &Demanded,
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+ const MachineRegisterInfo *MRI) {
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+ VSETVLIInfo Info = NewInfo;
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// If we don't use LMUL or the SEW/LMUL ratio, then adjust LMUL so that we
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// maintain the SEW/LMUL ratio. This allows us to eliminate VL toggles in more
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// places.
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- DemandedFields Demanded = getDemanded (MI, MRI, ST);
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if (!Demanded.LMUL && !Demanded.SEWLMULRatio && PrevInfo.isValid () &&
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!PrevInfo.isUnknown ()) {
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if (auto NewVLMul = RISCVVType::getSameRatioLMUL (
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PrevInfo.getSEW (), PrevInfo.getVLMUL (), Info.getSEW ()))
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Info.setVLMul (*NewVLMul);
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+ Demanded.LMUL = true ;
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}
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// If we only demand VL zeroness (i.e. vmv.s.x and vmv.x.s), then there are
@@ -1080,8 +1113,12 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
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// to prevent extending live range of an avl register operand.
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// TODO: We can probably relax this for immediates.
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if (Demanded.VLZeroness && !Demanded.VLAny && PrevInfo.isValid () &&
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- PrevInfo.hasEquallyZeroAVL (Info, *MRI) && Info.hasSameVLMAX (PrevInfo))
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+ PrevInfo.hasEquallyZeroAVL (Info, *MRI) && Info.hasSameVLMAX (PrevInfo)) {
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Info.setAVL (PrevInfo);
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+ Demanded.demandVL ();
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+ }
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+
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+ return Info;
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}
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// Given a state with which we evaluated MI (see transferBefore above for why
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