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[AMDGPU] Track physical VGPRs used for SGPR spills
Physical VGPRs used for SGPR spills need to be tracked independent of WWM reserved registers. The WWM reserved set contains extra registers allocated during WWM pre-allocation pass. This causes SGPR spills allocated after WWM pre-allocation to overlap with WWM register usage, e.g. if frame pointer is spilt during prologue/epilog insertion.
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3 files changed

+5
-3
lines changed

3 files changed

+5
-3
lines changed

llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -349,8 +349,9 @@ bool SIMachineFunctionInfo::allocatePhysicalVGPRForSGPRSpills(
349349
MBB.addLiveIn(LaneVGPR);
350350
MBB.sortUniqueLiveIns();
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}
352+
SpillPhysVGPRs.push_back(LaneVGPR);
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} else {
353-
LaneVGPR = WWMReservedRegs.back();
354+
LaneVGPR = SpillPhysVGPRs.back();
354355
}
355356

356357
SGPRSpillsToPhysicalVGPRLanes[FI].push_back(

llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -502,6 +502,7 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction,
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unsigned NumVirtualVGPRSpillLanes = 0;
503503
unsigned NumPhysicalVGPRSpillLanes = 0;
504504
SmallVector<Register, 2> SpillVGPRs;
505+
SmallVector<Register, 2> SpillPhysVGPRs;
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using WWMSpillsMap = MapVector<Register, int>;
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// To track the registers used in instructions that can potentially modify the
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// inactive lanes. The WWM instructions and the writelane instructions for

llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@ body: |
3939
; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR $vgpr5, $sgpr33, 12, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.72, addrspace 5)
4040
; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr4, $sgpr33, 16, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %stack.74, addrspace 5)
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; GCN-NEXT: $exec_lo = S_MOV_B32 killed $sgpr1
42-
; GCN-NEXT: $vgpr4 = SI_SPILL_S32_TO_VGPR $sgpr0, 4, undef $vgpr4
42+
; GCN-NEXT: $vgpr3 = SI_SPILL_S32_TO_VGPR $sgpr0, 4, undef $vgpr3
4343
; GCN-NEXT: $sgpr32 = frame-setup S_ADD_I32 $sgpr32, 24, implicit-def dead $scc
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; GCN-NEXT: renamable $vgpr5 = IMPLICIT_DEF
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; GCN-NEXT: $vgpr1 = SI_SPILL_S32_TO_VGPR $sgpr4, 0, $vgpr1
@@ -198,7 +198,7 @@ body: |
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; GCN-NEXT: $sgpr5 = SI_RESTORE_S32_FROM_VGPR $vgpr1, 1
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; GCN-NEXT: $sgpr4 = SI_RESTORE_S32_FROM_VGPR $vgpr1, 0
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; GCN-NEXT: KILL killed renamable $vgpr5
201-
; GCN-NEXT: $sgpr0 = SI_RESTORE_S32_FROM_VGPR $vgpr4, 4
201+
; GCN-NEXT: $sgpr0 = SI_RESTORE_S32_FROM_VGPR $vgpr3, 4
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; GCN-NEXT: $sgpr1 = S_XOR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec
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; GCN-NEXT: $vgpr1 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 0, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.69, addrspace 5)
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; GCN-NEXT: $vgpr2 = SCRATCH_LOAD_DWORD_SADDR $sgpr33, 4, 0, implicit $exec, implicit $flat_scr :: (load (s32) from %stack.70, addrspace 5)

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