Skip to content

Commit cf57ecd

Browse files
committed
Revert "[Flang][OpenMP] Disable lowering of omp.simd reductions in composites (#112686)"
Lowering of reductions in composite operations can now be re-enabled, since previous commits in this PR stack fix the MLIR representation produced and it no longer triggers a compiler crash during translation to LLVM IR. This reverts commit c44860c.
1 parent 58f02e5 commit cf57ecd

File tree

2 files changed

+27
-14
lines changed

2 files changed

+27
-14
lines changed

flang/lib/Lower/OpenMP/OpenMP.cpp

Lines changed: 6 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -2246,12 +2246,6 @@ static void genCompositeDistributeParallelDoSimd(
22462246
genSimdClauses(converter, semaCtx, simdItem->clauses, loc, simdClauseOps,
22472247
simdReductionSyms);
22482248

2249-
// TODO: Remove this after omp.simd reductions on composite constructs are
2250-
// supported.
2251-
simdClauseOps.reductionVars.clear();
2252-
simdClauseOps.reductionByref.clear();
2253-
simdClauseOps.reductionSyms.clear();
2254-
22552249
mlir::omp::LoopNestOperands loopNestClauseOps;
22562250
llvm::SmallVector<const semantics::Symbol *> iv;
22572251
genLoopNestClauses(converter, semaCtx, eval, simdItem->clauses, loc,
@@ -2273,7 +2267,9 @@ static void genCompositeDistributeParallelDoSimd(
22732267
wsloopOp.setComposite(/*val=*/true);
22742268

22752269
EntryBlockArgs simdArgs;
2276-
// TODO: Add private and reduction syms and vars.
2270+
// TODO: Add private syms and vars.
2271+
simdArgs.reduction.syms = simdReductionSyms;
2272+
simdArgs.reduction.vars = simdClauseOps.reductionVars;
22772273
auto simdOp =
22782274
genWrapperOp<mlir::omp::SimdOp>(converter, loc, simdClauseOps, simdArgs);
22792275
simdOp.setComposite(/*val=*/true);
@@ -2366,12 +2362,6 @@ static void genCompositeDoSimd(lower::AbstractConverter &converter,
23662362
genSimdClauses(converter, semaCtx, simdItem->clauses, loc, simdClauseOps,
23672363
simdReductionSyms);
23682364

2369-
// TODO: Remove this after omp.simd reductions on composite constructs are
2370-
// supported.
2371-
simdClauseOps.reductionVars.clear();
2372-
simdClauseOps.reductionByref.clear();
2373-
simdClauseOps.reductionSyms.clear();
2374-
23752365
// TODO: Support delayed privatization.
23762366
DataSharingProcessor dsp(converter, semaCtx, simdItem->clauses, eval,
23772367
/*shouldCollectPreDeterminedSymbols=*/true,
@@ -2395,7 +2385,9 @@ static void genCompositeDoSimd(lower::AbstractConverter &converter,
23952385
wsloopOp.setComposite(/*val=*/true);
23962386

23972387
EntryBlockArgs simdArgs;
2398-
// TODO: Add private and reduction syms and vars.
2388+
// TODO: Add private syms and vars.
2389+
simdArgs.reduction.syms = simdReductionSyms;
2390+
simdArgs.reduction.vars = simdClauseOps.reductionVars;
23992391
auto simdOp =
24002392
genWrapperOp<mlir::omp::SimdOp>(converter, loc, simdClauseOps, simdArgs);
24012393
simdOp.setComposite(/*val=*/true);

flang/test/Lower/OpenMP/wsloop-simd.f90

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -45,3 +45,24 @@ subroutine do_simd_simdlen()
4545
end do
4646
!$omp end do simd
4747
end subroutine do_simd_simdlen
48+
49+
! CHECK-LABEL: func.func @_QPdo_simd_reduction(
50+
subroutine do_simd_reduction()
51+
integer :: sum
52+
sum = 0
53+
! CHECK: omp.wsloop
54+
! CHECK-SAME: reduction(@[[RED_SYM:.*]] %{{.*}} -> %[[RED_OUTER:.*]] : !fir.ref<i32>)
55+
! CHECK-NEXT: omp.simd
56+
! CHECK-SAME: reduction(@[[RED_SYM]] %[[RED_OUTER]] -> %[[RED_INNER:.*]] : !fir.ref<i32>)
57+
! CHECK-NEXT: omp.loop_nest
58+
! CHECK: %[[RED_DECL:.*]]:2 = hlfir.declare %[[RED_INNER]]
59+
! CHECK: %[[RED:.*]] = fir.load %[[RED_DECL]]#0 : !fir.ref<i32>
60+
! CHECK: %[[RESULT:.*]] = arith.addi %[[RED]], %{{.*}} : i32
61+
! CHECK: hlfir.assign %[[RESULT]] to %[[RED_DECL]]#0 : i32, !fir.ref<i32>
62+
! CHECK-NEXT: omp.yield
63+
!$omp do simd reduction(+:sum)
64+
do index_ = 1, 10
65+
sum = sum + 1
66+
end do
67+
!$omp end do simd
68+
end subroutine do_simd_reduction

0 commit comments

Comments
 (0)