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[RISCV] Adjust tested vor ops for more stable tests. NFC.
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‎llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll

Lines changed: 44 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -17,9 +17,9 @@ define <vscale x 1 x i8> @vor_vx_nxv1i8_0(<vscale x 1 x i8> %va) {
1717
; CHECK-LABEL: vor_vx_nxv1i8_0:
1818
; CHECK: # %bb.0:
1919
; CHECK-NEXT: vsetvli a0, zero, e8,mf8,ta,mu
20-
; CHECK-NEXT: vor.vi v16, v16, -1
20+
; CHECK-NEXT: vor.vi v16, v16, -12
2121
; CHECK-NEXT: ret
22-
%head = insertelement <vscale x 1 x i8> undef, i8 -1, i32 0
22+
%head = insertelement <vscale x 1 x i8> undef, i8 -12, i32 0
2323
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
2424
%vc = or <vscale x 1 x i8> %va, %splat
2525
ret <vscale x 1 x i8> %vc
@@ -66,9 +66,9 @@ define <vscale x 2 x i8> @vor_vx_nxv2i8_0(<vscale x 2 x i8> %va) {
6666
; CHECK-LABEL: vor_vx_nxv2i8_0:
6767
; CHECK: # %bb.0:
6868
; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
69-
; CHECK-NEXT: vor.vi v16, v16, -1
69+
; CHECK-NEXT: vor.vi v16, v16, -12
7070
; CHECK-NEXT: ret
71-
%head = insertelement <vscale x 2 x i8> undef, i8 -1, i32 0
71+
%head = insertelement <vscale x 2 x i8> undef, i8 -12, i32 0
7272
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
7373
%vc = or <vscale x 2 x i8> %va, %splat
7474
ret <vscale x 2 x i8> %vc
@@ -115,9 +115,9 @@ define <vscale x 4 x i8> @vor_vx_nxv4i8_0(<vscale x 4 x i8> %va) {
115115
; CHECK-LABEL: vor_vx_nxv4i8_0:
116116
; CHECK: # %bb.0:
117117
; CHECK-NEXT: vsetvli a0, zero, e8,mf2,ta,mu
118-
; CHECK-NEXT: vor.vi v16, v16, -1
118+
; CHECK-NEXT: vor.vi v16, v16, -12
119119
; CHECK-NEXT: ret
120-
%head = insertelement <vscale x 4 x i8> undef, i8 -1, i32 0
120+
%head = insertelement <vscale x 4 x i8> undef, i8 -12, i32 0
121121
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
122122
%vc = or <vscale x 4 x i8> %va, %splat
123123
ret <vscale x 4 x i8> %vc
@@ -164,9 +164,9 @@ define <vscale x 8 x i8> @vor_vx_nxv8i8_0(<vscale x 8 x i8> %va) {
164164
; CHECK-LABEL: vor_vx_nxv8i8_0:
165165
; CHECK: # %bb.0:
166166
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
167-
; CHECK-NEXT: vor.vi v16, v16, -1
167+
; CHECK-NEXT: vor.vi v16, v16, -12
168168
; CHECK-NEXT: ret
169-
%head = insertelement <vscale x 8 x i8> undef, i8 -1, i32 0
169+
%head = insertelement <vscale x 8 x i8> undef, i8 -12, i32 0
170170
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
171171
%vc = or <vscale x 8 x i8> %va, %splat
172172
ret <vscale x 8 x i8> %vc
@@ -213,9 +213,9 @@ define <vscale x 16 x i8> @vor_vx_nxv16i8_0(<vscale x 16 x i8> %va) {
213213
; CHECK-LABEL: vor_vx_nxv16i8_0:
214214
; CHECK: # %bb.0:
215215
; CHECK-NEXT: vsetvli a0, zero, e8,m2,ta,mu
216-
; CHECK-NEXT: vor.vi v16, v16, -1
216+
; CHECK-NEXT: vor.vi v16, v16, -12
217217
; CHECK-NEXT: ret
218-
%head = insertelement <vscale x 16 x i8> undef, i8 -1, i32 0
218+
%head = insertelement <vscale x 16 x i8> undef, i8 -12, i32 0
219219
%splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
220220
%vc = or <vscale x 16 x i8> %va, %splat
221221
ret <vscale x 16 x i8> %vc
@@ -262,9 +262,9 @@ define <vscale x 32 x i8> @vor_vx_nxv32i8_0(<vscale x 32 x i8> %va) {
262262
; CHECK-LABEL: vor_vx_nxv32i8_0:
263263
; CHECK: # %bb.0:
264264
; CHECK-NEXT: vsetvli a0, zero, e8,m4,ta,mu
265-
; CHECK-NEXT: vor.vi v16, v16, -1
265+
; CHECK-NEXT: vor.vi v16, v16, -12
266266
; CHECK-NEXT: ret
267-
%head = insertelement <vscale x 32 x i8> undef, i8 -1, i32 0
267+
%head = insertelement <vscale x 32 x i8> undef, i8 -12, i32 0
268268
%splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
269269
%vc = or <vscale x 32 x i8> %va, %splat
270270
ret <vscale x 32 x i8> %vc
@@ -311,9 +311,9 @@ define <vscale x 64 x i8> @vor_vx_nxv64i8_0(<vscale x 64 x i8> %va) {
311311
; CHECK-LABEL: vor_vx_nxv64i8_0:
312312
; CHECK: # %bb.0:
313313
; CHECK-NEXT: vsetvli a0, zero, e8,m8,ta,mu
314-
; CHECK-NEXT: vor.vi v16, v16, -1
314+
; CHECK-NEXT: vor.vi v16, v16, -12
315315
; CHECK-NEXT: ret
316-
%head = insertelement <vscale x 64 x i8> undef, i8 -1, i32 0
316+
%head = insertelement <vscale x 64 x i8> undef, i8 -12, i32 0
317317
%splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
318318
%vc = or <vscale x 64 x i8> %va, %splat
319319
ret <vscale x 64 x i8> %vc
@@ -360,9 +360,9 @@ define <vscale x 1 x i16> @vor_vx_nxv1i16_0(<vscale x 1 x i16> %va) {
360360
; CHECK-LABEL: vor_vx_nxv1i16_0:
361361
; CHECK: # %bb.0:
362362
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
363-
; CHECK-NEXT: vor.vi v16, v16, -1
363+
; CHECK-NEXT: vor.vi v16, v16, -12
364364
; CHECK-NEXT: ret
365-
%head = insertelement <vscale x 1 x i16> undef, i16 -1, i32 0
365+
%head = insertelement <vscale x 1 x i16> undef, i16 -12, i32 0
366366
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
367367
%vc = or <vscale x 1 x i16> %va, %splat
368368
ret <vscale x 1 x i16> %vc
@@ -409,9 +409,9 @@ define <vscale x 2 x i16> @vor_vx_nxv2i16_0(<vscale x 2 x i16> %va) {
409409
; CHECK-LABEL: vor_vx_nxv2i16_0:
410410
; CHECK: # %bb.0:
411411
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
412-
; CHECK-NEXT: vor.vi v16, v16, -1
412+
; CHECK-NEXT: vor.vi v16, v16, -12
413413
; CHECK-NEXT: ret
414-
%head = insertelement <vscale x 2 x i16> undef, i16 -1, i32 0
414+
%head = insertelement <vscale x 2 x i16> undef, i16 -12, i32 0
415415
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
416416
%vc = or <vscale x 2 x i16> %va, %splat
417417
ret <vscale x 2 x i16> %vc
@@ -458,9 +458,9 @@ define <vscale x 4 x i16> @vor_vx_nxv4i16_0(<vscale x 4 x i16> %va) {
458458
; CHECK-LABEL: vor_vx_nxv4i16_0:
459459
; CHECK: # %bb.0:
460460
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
461-
; CHECK-NEXT: vor.vi v16, v16, -1
461+
; CHECK-NEXT: vor.vi v16, v16, -12
462462
; CHECK-NEXT: ret
463-
%head = insertelement <vscale x 4 x i16> undef, i16 -1, i32 0
463+
%head = insertelement <vscale x 4 x i16> undef, i16 -12, i32 0
464464
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
465465
%vc = or <vscale x 4 x i16> %va, %splat
466466
ret <vscale x 4 x i16> %vc
@@ -507,9 +507,9 @@ define <vscale x 8 x i16> @vor_vx_nxv8i16_0(<vscale x 8 x i16> %va) {
507507
; CHECK-LABEL: vor_vx_nxv8i16_0:
508508
; CHECK: # %bb.0:
509509
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
510-
; CHECK-NEXT: vor.vi v16, v16, -1
510+
; CHECK-NEXT: vor.vi v16, v16, -12
511511
; CHECK-NEXT: ret
512-
%head = insertelement <vscale x 8 x i16> undef, i16 -1, i32 0
512+
%head = insertelement <vscale x 8 x i16> undef, i16 -12, i32 0
513513
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
514514
%vc = or <vscale x 8 x i16> %va, %splat
515515
ret <vscale x 8 x i16> %vc
@@ -556,9 +556,9 @@ define <vscale x 16 x i16> @vor_vx_nxv16i16_0(<vscale x 16 x i16> %va) {
556556
; CHECK-LABEL: vor_vx_nxv16i16_0:
557557
; CHECK: # %bb.0:
558558
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
559-
; CHECK-NEXT: vor.vi v16, v16, -1
559+
; CHECK-NEXT: vor.vi v16, v16, -12
560560
; CHECK-NEXT: ret
561-
%head = insertelement <vscale x 16 x i16> undef, i16 -1, i32 0
561+
%head = insertelement <vscale x 16 x i16> undef, i16 -12, i32 0
562562
%splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
563563
%vc = or <vscale x 16 x i16> %va, %splat
564564
ret <vscale x 16 x i16> %vc
@@ -605,9 +605,9 @@ define <vscale x 32 x i16> @vor_vx_nxv32i16_0(<vscale x 32 x i16> %va) {
605605
; CHECK-LABEL: vor_vx_nxv32i16_0:
606606
; CHECK: # %bb.0:
607607
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
608-
; CHECK-NEXT: vor.vi v16, v16, -1
608+
; CHECK-NEXT: vor.vi v16, v16, -12
609609
; CHECK-NEXT: ret
610-
%head = insertelement <vscale x 32 x i16> undef, i16 -1, i32 0
610+
%head = insertelement <vscale x 32 x i16> undef, i16 -12, i32 0
611611
%splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
612612
%vc = or <vscale x 32 x i16> %va, %splat
613613
ret <vscale x 32 x i16> %vc
@@ -654,9 +654,9 @@ define <vscale x 1 x i32> @vor_vx_nxv1i32_0(<vscale x 1 x i32> %va) {
654654
; CHECK-LABEL: vor_vx_nxv1i32_0:
655655
; CHECK: # %bb.0:
656656
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
657-
; CHECK-NEXT: vor.vi v16, v16, -1
657+
; CHECK-NEXT: vor.vi v16, v16, -12
658658
; CHECK-NEXT: ret
659-
%head = insertelement <vscale x 1 x i32> undef, i32 -1, i32 0
659+
%head = insertelement <vscale x 1 x i32> undef, i32 -12, i32 0
660660
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
661661
%vc = or <vscale x 1 x i32> %va, %splat
662662
ret <vscale x 1 x i32> %vc
@@ -703,9 +703,9 @@ define <vscale x 2 x i32> @vor_vx_nxv2i32_0(<vscale x 2 x i32> %va) {
703703
; CHECK-LABEL: vor_vx_nxv2i32_0:
704704
; CHECK: # %bb.0:
705705
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
706-
; CHECK-NEXT: vor.vi v16, v16, -1
706+
; CHECK-NEXT: vor.vi v16, v16, -12
707707
; CHECK-NEXT: ret
708-
%head = insertelement <vscale x 2 x i32> undef, i32 -1, i32 0
708+
%head = insertelement <vscale x 2 x i32> undef, i32 -12, i32 0
709709
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
710710
%vc = or <vscale x 2 x i32> %va, %splat
711711
ret <vscale x 2 x i32> %vc
@@ -752,9 +752,9 @@ define <vscale x 4 x i32> @vor_vx_nxv4i32_0(<vscale x 4 x i32> %va) {
752752
; CHECK-LABEL: vor_vx_nxv4i32_0:
753753
; CHECK: # %bb.0:
754754
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
755-
; CHECK-NEXT: vor.vi v16, v16, -1
755+
; CHECK-NEXT: vor.vi v16, v16, -12
756756
; CHECK-NEXT: ret
757-
%head = insertelement <vscale x 4 x i32> undef, i32 -1, i32 0
757+
%head = insertelement <vscale x 4 x i32> undef, i32 -12, i32 0
758758
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
759759
%vc = or <vscale x 4 x i32> %va, %splat
760760
ret <vscale x 4 x i32> %vc
@@ -801,9 +801,9 @@ define <vscale x 8 x i32> @vor_vx_nxv8i32_0(<vscale x 8 x i32> %va) {
801801
; CHECK-LABEL: vor_vx_nxv8i32_0:
802802
; CHECK: # %bb.0:
803803
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
804-
; CHECK-NEXT: vor.vi v16, v16, -1
804+
; CHECK-NEXT: vor.vi v16, v16, -12
805805
; CHECK-NEXT: ret
806-
%head = insertelement <vscale x 8 x i32> undef, i32 -1, i32 0
806+
%head = insertelement <vscale x 8 x i32> undef, i32 -12, i32 0
807807
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
808808
%vc = or <vscale x 8 x i32> %va, %splat
809809
ret <vscale x 8 x i32> %vc
@@ -850,9 +850,9 @@ define <vscale x 16 x i32> @vor_vx_nxv16i32_0(<vscale x 16 x i32> %va) {
850850
; CHECK-LABEL: vor_vx_nxv16i32_0:
851851
; CHECK: # %bb.0:
852852
; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
853-
; CHECK-NEXT: vor.vi v16, v16, -1
853+
; CHECK-NEXT: vor.vi v16, v16, -12
854854
; CHECK-NEXT: ret
855-
%head = insertelement <vscale x 16 x i32> undef, i32 -1, i32 0
855+
%head = insertelement <vscale x 16 x i32> undef, i32 -12, i32 0
856856
%splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
857857
%vc = or <vscale x 16 x i32> %va, %splat
858858
ret <vscale x 16 x i32> %vc
@@ -906,9 +906,9 @@ define <vscale x 1 x i64> @vor_vx_nxv1i64_0(<vscale x 1 x i64> %va) {
906906
; CHECK-LABEL: vor_vx_nxv1i64_0:
907907
; CHECK: # %bb.0:
908908
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
909-
; CHECK-NEXT: vor.vi v16, v16, -1
909+
; CHECK-NEXT: vor.vi v16, v16, -12
910910
; CHECK-NEXT: ret
911-
%head = insertelement <vscale x 1 x i64> undef, i64 -1, i32 0
911+
%head = insertelement <vscale x 1 x i64> undef, i64 -12, i32 0
912912
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
913913
%vc = or <vscale x 1 x i64> %va, %splat
914914
ret <vscale x 1 x i64> %vc
@@ -962,9 +962,9 @@ define <vscale x 2 x i64> @vor_vx_nxv2i64_0(<vscale x 2 x i64> %va) {
962962
; CHECK-LABEL: vor_vx_nxv2i64_0:
963963
; CHECK: # %bb.0:
964964
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
965-
; CHECK-NEXT: vor.vi v16, v16, -1
965+
; CHECK-NEXT: vor.vi v16, v16, -12
966966
; CHECK-NEXT: ret
967-
%head = insertelement <vscale x 2 x i64> undef, i64 -1, i32 0
967+
%head = insertelement <vscale x 2 x i64> undef, i64 -12, i32 0
968968
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
969969
%vc = or <vscale x 2 x i64> %va, %splat
970970
ret <vscale x 2 x i64> %vc
@@ -1018,9 +1018,9 @@ define <vscale x 4 x i64> @vor_vx_nxv4i64_0(<vscale x 4 x i64> %va) {
10181018
; CHECK-LABEL: vor_vx_nxv4i64_0:
10191019
; CHECK: # %bb.0:
10201020
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
1021-
; CHECK-NEXT: vor.vi v16, v16, -1
1021+
; CHECK-NEXT: vor.vi v16, v16, -12
10221022
; CHECK-NEXT: ret
1023-
%head = insertelement <vscale x 4 x i64> undef, i64 -1, i32 0
1023+
%head = insertelement <vscale x 4 x i64> undef, i64 -12, i32 0
10241024
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
10251025
%vc = or <vscale x 4 x i64> %va, %splat
10261026
ret <vscale x 4 x i64> %vc
@@ -1074,9 +1074,9 @@ define <vscale x 8 x i64> @vor_vx_nxv8i64_0(<vscale x 8 x i64> %va) {
10741074
; CHECK-LABEL: vor_vx_nxv8i64_0:
10751075
; CHECK: # %bb.0:
10761076
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
1077-
; CHECK-NEXT: vor.vi v16, v16, -1
1077+
; CHECK-NEXT: vor.vi v16, v16, -12
10781078
; CHECK-NEXT: ret
1079-
%head = insertelement <vscale x 8 x i64> undef, i64 -1, i32 0
1079+
%head = insertelement <vscale x 8 x i64> undef, i64 -12, i32 0
10801080
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
10811081
%vc = or <vscale x 8 x i64> %va, %splat
10821082
ret <vscale x 8 x i64> %vc

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