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adding OPCode and Intrinsic
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llvm/include/llvm/IR/IntrinsicsDirectX.td

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@@ -35,6 +35,9 @@ def int_dx_typedBufferLoad_checkbit
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def int_dx_typedBufferStore
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: DefaultAttrsIntrinsic<[], [llvm_any_ty, llvm_i32_ty, llvm_anyvector_ty]>;
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def int_dx_updateCounter
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: DefaultAttrsIntrinsic<[], [llvm_any_ty, llvm_anyint_ty]>;
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// Cast between target extension handle types and dxil-style opaque handles
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def int_dx_cast_handle : Intrinsic<[llvm_any_ty], [llvm_any_ty]>;
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llvm/lib/Target/DirectX/DXIL.td

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@@ -730,6 +730,16 @@ def BufferStore : DXILOp<69, bufferStore> {
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let stages = [Stages<DXIL1_0, [all_stages]>];
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}
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def UpdateCounter : DXILOp<70, bufferUpdateCounter> {
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let Doc = "increments/decrements a buffer counter";
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let LLVMIntrinsic = int_dx_updateCounter;
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let arguments = [
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HandleTy, Int8Ty
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];
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let result = VoidTy;
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let stages = [Stages<DXIL1_0, [all_stages]>];
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}
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def CheckAccessFullyMapped : DXILOp<71, checkAccessFullyMapped> {
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let Doc = "checks whether a Sample, Gather, or Load operation "
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"accessed mapped tiles in a tiled resource";
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@@ -0,0 +1,13 @@
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; RUN: opt -S -dxil-op-lower %s | FileCheck %s
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target triple = "dxil-pc-shadermodel6.6-compute"
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define void @loadv4f32() {
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%buffer = call target("dx.TypedBuffer", <4 x float>, 0, 0, 0)
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@llvm.dx.handle.fromBinding.tdx.TypedBuffer_v4f32_0_0_0(
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i32 0, i32 0, i32 1, i32 0, i1 false)
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call void @llvm.dx.updateCounter(target("dx.TypedBuffer", <4 x float>, 0, 0, 0) %buffer, i8 -1)
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ret void
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}

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