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koachankoachan
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Reapply "[SPARC] Use umulxhi to do extending 64x64->128 multiply when we have VIS3" (#135897) (#136475)
Update the tests to reflect the change in instruction ordering. Otherwise there are no changes from the previous commit. This reverts commit 5e9650e.
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-2
lines changed

5 files changed

+150
-2
lines changed

‎llvm/lib/Target/Sparc/SparcISelLowering.cpp

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1857,8 +1857,10 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
18571857
if (Subtarget->is64Bit()) {
18581858
setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
18591859
setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
1860-
setOperationAction(ISD::MULHU, MVT::i64, Expand);
1861-
setOperationAction(ISD::MULHS, MVT::i64, Expand);
1860+
setOperationAction(ISD::MULHU, MVT::i64,
1861+
Subtarget->isVIS3() ? Legal : Expand);
1862+
setOperationAction(ISD::MULHS, MVT::i64,
1863+
Subtarget->isVIS3() ? Legal : Expand);
18621864

18631865
setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
18641866
setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);

‎llvm/lib/Target/Sparc/SparcInstrVIS.td

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -295,6 +295,16 @@ def : Pat<(f32 fpnegimm0), (FNEGS (FZEROS))>;
295295
let Predicates = [HasVIS3] in {
296296
def : Pat<(i64 (adde i64:$lhs, i64:$rhs)), (ADDXCCC $lhs, $rhs)>;
297297

298+
def : Pat<(i64 (mulhu i64:$lhs, i64:$rhs)), (UMULXHI $lhs, $rhs)>;
299+
// Signed "MULXHI".
300+
// Based on the formula presented in OSA2011 §7.140, but with bitops to select
301+
// the values to be added.
302+
// TODO: This expansion should probably be moved to DAG legalization phase.
303+
def : Pat<(i64 (mulhs i64:$lhs, i64:$rhs)),
304+
(SUBrr (UMULXHI $lhs, $rhs),
305+
(ADDrr (ANDrr (SRAXri $lhs, 63), $rhs),
306+
(ANDrr (SRAXri $rhs, 63), $lhs)))>;
307+
298308
def : Pat<(i64 (ctlz i64:$src)), (LZCNT $src)>;
299309
def : Pat<(i64 (ctlz_zero_undef i64:$src)), (LZCNT $src)>;
300310
// 32-bit LZCNT.

‎llvm/test/CodeGen/SPARC/multiply-extension.ll

Lines changed: 59 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,59 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc < %s -mtriple=sparcv9 | FileCheck %s -check-prefix=V9
3+
; RUN: llc < %s -mtriple=sparcv9 -mattr=+vis3 | FileCheck %s -check-prefix=VIS3
4+
5+
define i128 @signed_multiply_extend(i64 %0, i64 %1) nounwind {
6+
; V9-LABEL: signed_multiply_extend:
7+
; V9: ! %bb.0:
8+
; V9-NEXT: save %sp, -176, %sp
9+
; V9-NEXT: mov %i1, %o1
10+
; V9-NEXT: mov %i0, %o3
11+
; V9-NEXT: srax %i0, 63, %o2
12+
; V9-NEXT: call __multi3
13+
; V9-NEXT: srax %i1, 63, %o0
14+
; V9-NEXT: mov %o0, %i0
15+
; V9-NEXT: ret
16+
; V9-NEXT: restore %g0, %o1, %o1
17+
;
18+
; VIS3-LABEL: signed_multiply_extend:
19+
; VIS3: ! %bb.0:
20+
; VIS3-NEXT: srax %o0, 63, %o2
21+
; VIS3-NEXT: and %o2, %o1, %o2
22+
; VIS3-NEXT: srax %o1, 63, %o3
23+
; VIS3-NEXT: and %o3, %o0, %o3
24+
; VIS3-NEXT: add %o3, %o2, %o2
25+
; VIS3-NEXT: umulxhi %o1, %o0, %o3
26+
; VIS3-NEXT: sub %o3, %o2, %o2
27+
; VIS3-NEXT: mulx %o1, %o0, %o1
28+
; VIS3-NEXT: retl
29+
; VIS3-NEXT: mov %o2, %o0
30+
%3 = sext i64 %0 to i128
31+
%4 = sext i64 %1 to i128
32+
%5 = mul nsw i128 %4, %3
33+
ret i128 %5
34+
}
35+
36+
define i128 @unsigned_multiply_extend(i64 %0, i64 %1) nounwind {
37+
; V9-LABEL: unsigned_multiply_extend:
38+
; V9: ! %bb.0:
39+
; V9-NEXT: save %sp, -176, %sp
40+
; V9-NEXT: mov %i1, %o1
41+
; V9-NEXT: mov %i0, %o3
42+
; V9-NEXT: mov %g0, %o0
43+
; V9-NEXT: call __multi3
44+
; V9-NEXT: mov %g0, %o2
45+
; V9-NEXT: mov %o0, %i0
46+
; V9-NEXT: ret
47+
; V9-NEXT: restore %g0, %o1, %o1
48+
;
49+
; VIS3-LABEL: unsigned_multiply_extend:
50+
; VIS3: ! %bb.0:
51+
; VIS3-NEXT: umulxhi %o1, %o0, %o2
52+
; VIS3-NEXT: mulx %o1, %o0, %o1
53+
; VIS3-NEXT: retl
54+
; VIS3-NEXT: mov %o2, %o0
55+
%3 = zext i64 %0 to i128
56+
%4 = zext i64 %1 to i128
57+
%5 = mul nuw i128 %4, %3
58+
ret i128 %5
59+
}

‎llvm/test/CodeGen/SPARC/smulo-128-legalisation-lowering.ll

Lines changed: 44 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc < %s -mtriple=sparc-unknown-linux-gnu | FileCheck %s --check-prefixes=SPARC
33
; RUN: llc < %s -mtriple=sparc64-unknown-linux-gnu | FileCheck %s --check-prefixes=SPARC64
4+
; RUN: llc < %s -mtriple=sparc64-unknown-linux-gnu -mattr=vis3 | FileCheck %s --check-prefixes=SPARC64-VIS3
45

56
define { i128, i8 } @muloti_test(i128 %l, i128 %r) nounwind {
67
; SPARC-LABEL: muloti_test:
@@ -213,6 +214,49 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) nounwind {
213214
; SPARC64-NEXT: srl %i3, 0, %i2
214215
; SPARC64-NEXT: ret
215216
; SPARC64-NEXT: restore
217+
;
218+
; SPARC64-VIS3-LABEL: muloti_test:
219+
; SPARC64-VIS3: .register %g2, #scratch
220+
; SPARC64-VIS3-NEXT: .register %g3, #scratch
221+
; SPARC64-VIS3-NEXT: ! %bb.0: ! %start
222+
; SPARC64-VIS3-NEXT: save %sp, -128, %sp
223+
; SPARC64-VIS3-NEXT: mov %g0, %i5
224+
; SPARC64-VIS3-NEXT: umulxhi %i0, %i3, %i4
225+
; SPARC64-VIS3-NEXT: srax %i0, 63, %g2
226+
; SPARC64-VIS3-NEXT: mulx %g2, %i3, %g3
227+
; SPARC64-VIS3-NEXT: add %i4, %g3, %i4
228+
; SPARC64-VIS3-NEXT: umulxhi %i1, %i3, %g3
229+
; SPARC64-VIS3-NEXT: mulx %i0, %i3, %g4
230+
; SPARC64-VIS3-NEXT: addcc %g4, %g3, %g3
231+
; SPARC64-VIS3-NEXT: addxccc %i4, %g0, %g4
232+
; SPARC64-VIS3-NEXT: umulxhi %i1, %i2, %i4
233+
; SPARC64-VIS3-NEXT: srax %i2, 63, %g5
234+
; SPARC64-VIS3-NEXT: mulx %i1, %g5, %l0
235+
; SPARC64-VIS3-NEXT: add %i4, %l0, %l0
236+
; SPARC64-VIS3-NEXT: mulx %i1, %i2, %i4
237+
; SPARC64-VIS3-NEXT: addcc %i4, %g3, %i4
238+
; SPARC64-VIS3-NEXT: addxccc %l0, %g0, %g3
239+
; SPARC64-VIS3-NEXT: srax %g3, 63, %l0
240+
; SPARC64-VIS3-NEXT: addcc %g4, %g3, %g3
241+
; SPARC64-VIS3-NEXT: srax %g4, 63, %g4
242+
; SPARC64-VIS3-NEXT: addxccc %g4, %l0, %g4
243+
; SPARC64-VIS3-NEXT: and %g5, %i0, %g5
244+
; SPARC64-VIS3-NEXT: and %g2, %i2, %g2
245+
; SPARC64-VIS3-NEXT: add %g2, %g5, %g2
246+
; SPARC64-VIS3-NEXT: umulxhi %i0, %i2, %g5
247+
; SPARC64-VIS3-NEXT: sub %g5, %g2, %g2
248+
; SPARC64-VIS3-NEXT: mulx %i0, %i2, %i0
249+
; SPARC64-VIS3-NEXT: addcc %i0, %g3, %i0
250+
; SPARC64-VIS3-NEXT: addxccc %g2, %g4, %i2
251+
; SPARC64-VIS3-NEXT: srax %i4, 63, %g2
252+
; SPARC64-VIS3-NEXT: xor %i2, %g2, %i2
253+
; SPARC64-VIS3-NEXT: xor %i0, %g2, %i0
254+
; SPARC64-VIS3-NEXT: or %i0, %i2, %i0
255+
; SPARC64-VIS3-NEXT: movrnz %i0, 1, %i5
256+
; SPARC64-VIS3-NEXT: mulx %i1, %i3, %i1
257+
; SPARC64-VIS3-NEXT: srl %i5, 0, %i2
258+
; SPARC64-VIS3-NEXT: ret
259+
; SPARC64-VIS3-NEXT: restore %g0, %i4, %o0
216260
start:
217261
%0 = tail call { i128, i1 } @llvm.smul.with.overflow.i128(i128 %l, i128 %r)
218262
%1 = extractvalue { i128, i1 } %0, 0

‎llvm/test/CodeGen/SPARC/umulo-128-legalisation-lowering.ll

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc < %s -mtriple=sparc-unknown-linux-gnu | FileCheck %s --check-prefixes=SPARC
33
; RUN: llc < %s -mtriple=sparc64-unknown-linux-gnu | FileCheck %s --check-prefixes=SPARC64
4+
; RUN: llc < %s -mtriple=sparc64-unknown-linux-gnu -mattr=vis3 | FileCheck %s --check-prefixes=SPARC64-VIS3
45

56
define { i128, i8 } @muloti_test(i128 %l, i128 %r) nounwind {
67
; SPARC-LABEL: muloti_test:
@@ -199,6 +200,38 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) nounwind {
199200
; SPARC64-NEXT: srl %i1, 0, %i2
200201
; SPARC64-NEXT: ret
201202
; SPARC64-NEXT: restore %g0, %o1, %o1
203+
;
204+
; SPARC64-VIS3-LABEL: muloti_test:
205+
; SPARC64-VIS3: .register %g2, #scratch
206+
; SPARC64-VIS3-NEXT: .register %g3, #scratch
207+
; SPARC64-VIS3-NEXT: ! %bb.0: ! %start
208+
; SPARC64-VIS3-NEXT: save %sp, -128, %sp
209+
; SPARC64-VIS3-NEXT: mov %g0, %i5
210+
; SPARC64-VIS3-NEXT: mov %g0, %g2
211+
; SPARC64-VIS3-NEXT: mov %g0, %g3
212+
; SPARC64-VIS3-NEXT: mov %g0, %g4
213+
; SPARC64-VIS3-NEXT: mov %g0, %g5
214+
; SPARC64-VIS3-NEXT: mulx %i2, %i1, %i4
215+
; SPARC64-VIS3-NEXT: mulx %i0, %i3, %l0
216+
; SPARC64-VIS3-NEXT: add %l0, %i4, %i4
217+
; SPARC64-VIS3-NEXT: umulxhi %i1, %i3, %l0
218+
; SPARC64-VIS3-NEXT: add %l0, %i4, %i4
219+
; SPARC64-VIS3-NEXT: cmp %i4, %l0
220+
; SPARC64-VIS3-NEXT: movrnz %i2, 1, %g2
221+
; SPARC64-VIS3-NEXT: movrnz %i0, 1, %g3
222+
; SPARC64-VIS3-NEXT: and %g3, %g2, %g2
223+
; SPARC64-VIS3-NEXT: umulxhi %i0, %i3, %i0
224+
; SPARC64-VIS3-NEXT: movrnz %i0, 1, %g4
225+
; SPARC64-VIS3-NEXT: movcs %xcc, 1, %i5
226+
; SPARC64-VIS3-NEXT: or %g2, %g4, %i0
227+
; SPARC64-VIS3-NEXT: umulxhi %i2, %i1, %i2
228+
; SPARC64-VIS3-NEXT: movrnz %i2, 1, %g5
229+
; SPARC64-VIS3-NEXT: or %i0, %g5, %i0
230+
; SPARC64-VIS3-NEXT: or %i0, %i5, %i0
231+
; SPARC64-VIS3-NEXT: mulx %i1, %i3, %i1
232+
; SPARC64-VIS3-NEXT: srl %i0, 0, %i2
233+
; SPARC64-VIS3-NEXT: ret
234+
; SPARC64-VIS3-NEXT: restore %g0, %i4, %o0
202235
start:
203236
%0 = tail call { i128, i1 } @llvm.umul.with.overflow.i128(i128 %l, i128 %r)
204237
%1 = extractvalue { i128, i1 } %0, 0

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