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mattardemahesh-attarde
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update clr
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‎clang/lib/Headers/CMakeLists.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -156,6 +156,7 @@ set(x86_files
156156
avx10_2_512satcvtintrin.h
157157
avx10_2bf16intrin.h
158158
avx10_2convertintrin.h
159+
avx10_2copyintrin.h
159160
avx10_2minmaxintrin.h
160161
avx10_2niintrin.h
161162
avx10_2satcvtdsintrin.h

‎clang/lib/Headers/avx10_2copyintrin.h

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,34 @@
1+
/*===---- avx10_2copyintrin.h - AVX10.2 Copy intrinsics -------------------===
2+
*
3+
* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4+
* See https://llvm.org/LICENSE.txt for license information.
5+
* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6+
*
7+
*===-----------------------------------------------------------------------===
8+
*/
9+
#ifndef __IMMINTRIN_H
10+
#error \
11+
"Never use <avx10_2copyintrin.h> directly; include <immintrin.h> instead."
12+
#endif // __IMMINTRIN_H
13+
14+
#ifndef __AVX10_2COPYINTRIN_H
15+
#define __AVX10_2COPYINTRIN_H
16+
17+
/* Define the default attributes for the functions in this file. */
18+
#define __DEFAULT_FN_ATTRS128 \
19+
__attribute__((__always_inline__, __nodebug__, __target__("avx10.2-256"), \
20+
__min_vector_width__(128)))
21+
22+
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_move_epi32(__m128i __A) {
23+
return (__m128i)__builtin_shufflevector(
24+
(__v4si)__A, (__v4si)_mm_setzero_si128(), 0, 4, 4, 4);
25+
}
26+
27+
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_move_epi16(__m128i __A) {
28+
return (__m128i)__builtin_shufflevector(
29+
(__v8hi)__A, (__v8hi)_mm_setzero_si128(), 0, 8, 8, 8, 8, 8, 8, 8);
30+
}
31+
32+
#undef __DEFAULT_FN_ATTRS128
33+
34+
#endif // __AVX10_2COPYINTRIN_H

‎clang/lib/Headers/immintrin.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -651,6 +651,7 @@ _storebe_i64(void * __P, long long __D) {
651651
#if !defined(__SCE__) || __has_feature(modules) || defined(__AVX10_2__)
652652
#include <avx10_2bf16intrin.h>
653653
#include <avx10_2convertintrin.h>
654+
#include <avx10_2copyintrin.h>
654655
#include <avx10_2minmaxintrin.h>
655656
#include <avx10_2niintrin.h>
656657
#include <avx10_2satcvtdsintrin.h>

‎clang/test/CodeGen/X86/avx512copy-builtins.c

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,17 @@
1+
// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=x86_64-unknown-unknown -target-feature +avx10.2-512 \
2+
// RUN: -emit-llvm -o - -Wall -Werror -pedantic -Wno-gnu-statement-expression | FileCheck %s
3+
4+
#include <immintrin.h>
5+
#include <stddef.h>
6+
7+
__m128i test_mm_move_epi32(__m128i A) {
8+
// CHECK-LABEL: test_mm_move_epi32
9+
// CHECK: shufflevector <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> <i32 0, i32 4, i32 4, i32 4>
10+
return _mm_move_epi32(A);
11+
}
12+
13+
__m128i test_mm_move_epi16(__m128i A) {
14+
// CHECK-LABEL: test_mm_move_epi16
15+
// CHECK: shufflevector <8 x i16> %{{.*}}, <8 x i16> %{{.*}}, <8 x i32> <i32 0, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8>
16+
return _mm_move_epi16(A);
17+
}

‎llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -12348,7 +12348,7 @@ static SDValue lowerShuffleAsElementInsertion(
1234812348
}
1234912349
V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
1235012350
} else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
12351-
EltVT == MVT::i16) {
12351+
(EltVT == MVT::i16 && !Subtarget.hasAVX10_2())) {
1235212352
// Either not inserting from the low element of the input or the input
1235312353
// element size is too small to use VZEXT_MOVL to clear the high bits.
1235412354
return SDValue();
@@ -38342,7 +38342,8 @@ static bool matchUnaryShuffle(MVT MaskVT, ArrayRef<int> Mask,
3834238342

3834338343
// Match against a VZEXT_MOVL instruction, SSE1 only supports 32-bits (MOVSS).
3834438344
if (((MaskEltSize == 32) || (MaskEltSize == 64 && Subtarget.hasSSE2()) ||
38345-
(MaskEltSize == 16 && Subtarget.hasFP16())) &&
38345+
(MaskEltSize == 16 &&
38346+
(Subtarget.hasFP16() || Subtarget.hasAVX10_2()))) &&
3834638347
isUndefOrEqual(Mask[0], 0) &&
3834738348
isUndefOrZeroInRange(Mask, 1, NumMaskElts - 1)) {
3834838349
Shuffle = X86ISD::VZEXT_MOVL;

‎llvm/lib/Target/X86/X86InstrAVX10.td

Lines changed: 64 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1537,3 +1537,67 @@ defm VFNMADD132NEPBF16 : avx10_fma3p_132_bf16<0x9C, "vfnmadd132nepbf16", X86any_
15371537
defm VFNMSUB132NEPBF16 : avx10_fma3p_132_bf16<0x9E, "vfnmsub132nepbf16", X86any_Fnmsub,
15381538
X86Fnmsub, SchedWriteFMA>;
15391539
}
1540+
1541+
//-------------------------------------------------
1542+
// AVX10 MOVZXC (COPY) instructions
1543+
//-------------------------------------------------
1544+
let Predicates = [HasAVX10_2] in {
1545+
def VMOVZPDILo2PDIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1546+
(ins VR128X:$src),
1547+
"vmovd\t{$src, $dst|$dst, $src}",
1548+
[(set VR128X:$dst, (v4i32 (X86vzmovl
1549+
(v4i32 VR128X:$src))))]>, EVEX,
1550+
Sched<[WriteVecMoveFromGpr]>;
1551+
1552+
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
1553+
def VMOVZPDILo2PDIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1554+
(ins i32mem:$src),
1555+
"vmovd\t{$src, $dst|$dst, $src}", []>, EVEX,
1556+
EVEX_CD8<32, CD8VT1>,
1557+
Sched<[WriteVecLoad]>;
1558+
1559+
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
1560+
def VMOVZPDILo2PDIZmr : AVX512PDI<0xD6, MRMDestMem, (outs),
1561+
(ins i32mem:$dst, VR128X:$src),
1562+
"vmovd\t{$src, $dst|$dst, $src}", []>, EVEX,
1563+
EVEX_CD8<32, CD8VT1>,
1564+
Sched<[WriteVecStore]>;
1565+
1566+
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
1567+
def VMOVZPDILo2PDIZrr2 : AVX512PDI<0xD6, MRMSrcReg, (outs VR128X:$dst),
1568+
(ins VR128X:$src),
1569+
"vmovd\t{$src, $dst|$dst, $src}", []>, EVEX,
1570+
Sched<[WriteVecMoveFromGpr]>;
1571+
def : InstAlias<"vmovd.s\t{$src, $dst|$dst, $src}",
1572+
(VMOVZPDILo2PDIZrr2 VR128X:$dst, VR128X:$src), 0>;
1573+
1574+
def VMOVZPWILo2PWIZrr : AVX512XSI<0x6E, MRMSrcReg, (outs VR128X:$dst),
1575+
(ins VR128X:$src),
1576+
"vmovw\t{$src, $dst|$dst, $src}",
1577+
[(set VR128X:$dst, (v8i16 (X86vzmovl
1578+
(v8i16 VR128X:$src))))]>, EVEX, T_MAP5,
1579+
Sched<[WriteVecMoveFromGpr]>;
1580+
1581+
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
1582+
def VMOVZPWILo2PWIZrm : AVX512XSI<0x6E, MRMSrcMem, (outs VR128X:$dst),
1583+
(ins i16mem:$src),
1584+
"vmovw\t{$src, $dst|$dst, $src}", []>, EVEX,
1585+
EVEX_CD8<16, CD8VT1>, T_MAP5,
1586+
Sched<[WriteVecLoad]>;
1587+
1588+
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
1589+
def VMOVZPWILo2PWIZmr : AVX512XSI<0x7E, MRMDestMem, (outs),
1590+
(ins i32mem:$dst, VR128X:$src),
1591+
"vmovw\t{$src, $dst|$dst, $src}", []>, EVEX,
1592+
EVEX_CD8<16, CD8VT1>, T_MAP5,
1593+
Sched<[WriteVecStore]>;
1594+
1595+
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
1596+
def VMOVZPWILo2PWIZrr2 : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1597+
(ins VR128X:$src),
1598+
"vmovw\t{$src, $dst|$dst, $src}",
1599+
[]>, EVEX, T_MAP5,
1600+
Sched<[WriteVecMoveFromGpr]>;
1601+
def : InstAlias<"vmovw.s\t{$src, $dst|$dst, $src}",
1602+
(VMOVZPWILo2PWIZrr2 VR128X:$dst, VR128X:$src), 0>;
1603+
}

‎llvm/test/CodeGen/X86/avx512copy-intrinsics.ll

Lines changed: 35 additions & 0 deletions
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@@ -0,0 +1,35 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx10.2-256 | FileCheck %s --check-prefixes=AVX102
3+
; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx512f | FileCheck %s --check-prefixes=NOAVX512MOVZXC
4+
5+
define <4 x i32> @test_mm_move_epi32(<4 x i32> %a0) nounwind {
6+
; AVX102-LABEL: test_mm_move_epi32:
7+
; AVX102: # %bb.0:
8+
; AVX102-NEXT: vmovd %xmm0, %xmm0 # encoding: [0x62,0xf1,0x7e,0x08,0x7e,0xc0]
9+
; AVX102-NEXT: retq # encoding: [0xc3]
10+
;
11+
; NOAVX512MOVZXC-LABEL: test_mm_move_epi32:
12+
; NOAVX512MOVZXC: # %bb.0:
13+
; NOAVX512MOVZXC-NEXT: vxorps %xmm1, %xmm1, %xmm1 # encoding: [0xc5,0xf0,0x57,0xc9]
14+
; NOAVX512MOVZXC-NEXT: vblendps $1, %xmm0, %xmm1, %xmm0 # encoding: [0xc4,0xe3,0x71,0x0c,0xc0,0x01]
15+
; NOAVX512MOVZXC-NEXT: # xmm0 = xmm0[0],xmm1[1,2,3]
16+
; NOAVX512MOVZXC-NEXT: retq # encoding: [0xc3]
17+
%res = shufflevector <4 x i32> %a0, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 4, i32 4, i32 4>
18+
ret <4 x i32> %res
19+
}
20+
21+
define <8 x i16> @test_mm_move_epi16(<8 x i16> %a0) nounwind {
22+
; AVX102-LABEL: test_mm_move_epi16:
23+
; AVX102: # %bb.0:
24+
; AVX102-NEXT: vmovw %xmm0, %xmm0 # encoding: [0x62,0xf5,0x7e,0x08,0x6e,0xc0]
25+
; AVX102-NEXT: retq # encoding: [0xc3]
26+
;
27+
; NOAVX512MOVZXC-LABEL: test_mm_move_epi16:
28+
; NOAVX512MOVZXC: # %bb.0:
29+
; NOAVX512MOVZXC-NEXT: vpxor %xmm1, %xmm1, %xmm1 # encoding: [0xc5,0xf1,0xef,0xc9]
30+
; NOAVX512MOVZXC-NEXT: vpblendw $1, %xmm0, %xmm1, %xmm0 # encoding: [0xc4,0xe3,0x71,0x0e,0xc0,0x01]
31+
; NOAVX512MOVZXC-NEXT: # xmm0 = xmm0[0],xmm1[1,2,3,4,5,6,7]
32+
; NOAVX512MOVZXC-NEXT: retq # encoding: [0xc3]
33+
%res = shufflevector <8 x i16> %a0, <8 x i16> zeroinitializer, <8 x i32> <i32 0, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8>
34+
ret <8 x i16> %res
35+
}

‎llvm/test/MC/Disassembler/X86/avx10.2-copy-32.txt

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,34 @@
1+
# RUN: llvm-mc --disassemble %s -triple=i386 | FileCheck %s --check-prefixes=ATT
2+
# RUN: llvm-mc --disassemble %s -triple=i386 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
3+
4+
# ATT: vmovd (%ecx), %xmm5
5+
# INTEL: vmovd xmm5, dword ptr [ecx]
6+
0x62 0xf1 0x7e 0x08 0x7e 0x29
7+
8+
# ATT: vmovd %xmm5, (%ecx)
9+
# INTEL: vmovd dword ptr [ecx], xmm5
10+
0x62 0xf1 0x7d 0x08 0xd6 0x29
11+
12+
# ATT: vmovd %xmm2, %xmm1
13+
# INTEL: vmovd xmm1, xmm2
14+
0x62 0xf1 0x7e 0x08 0x7e 0xca
15+
16+
# ATT: vmovd %xmm2, %xmm1
17+
# INTEL: vmovd xmm1, xmm2
18+
0x62 0xf1 0x7d 0x08 0xd6 0xca
19+
20+
# ATT: vmovw %xmm5, (%ecx)
21+
# INTEL: vmovw dword ptr [ecx], xmm5
22+
0x62 0xf5 0x7e 0x08 0x7e 0x29
23+
24+
# ATT: vmovw (%ecx), %xmm5
25+
# INTEL: vmovw xmm5, word ptr [ecx]
26+
0x62 0xf5 0x7e 0x08 0x6e 0x29
27+
28+
# ATT: vmovw %xmm2, %xmm1
29+
# INTEL: vmovw xmm1, xmm2
30+
0x62 0xf5 0x7e 0x08 0x6e 0xca
31+
32+
# ATT: vmovw %xmm2, %xmm1
33+
# INTEL: vmovw xmm1, xmm2
34+
0x62 0xf5 0x7e 0x08 0x7e 0xca

‎llvm/test/MC/Disassembler/X86/avx10.2-copy-64.txt

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,34 @@
1+
# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
2+
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
3+
4+
# ATT: vmovd (%rcx), %xmm29
5+
# INTEL: vmovd xmm29, dword ptr [rcx]
6+
0x62 0x61 0x7e 0x08 0x7e 0x29
7+
8+
# ATT: vmovd %xmm29, (%rcx)
9+
# INTEL: vmovd dword ptr [rcx], xmm29
10+
0x62 0x61 0x7d 0x08 0xd6 0x29
11+
12+
# ATT: vmovd %xmm22, %xmm21
13+
# INTEL: vmovd xmm21, xmm22
14+
0x62 0xa1 0x7e 0x08 0x7e 0xee
15+
16+
# ATT: vmovd %xmm22, %xmm21
17+
# INTEL: vmovd xmm21, xmm22
18+
0x62 0xa1 0x7d 0x08 0xd6 0xee
19+
20+
# ATT: vmovw %xmm29, (%rcx)
21+
# INTEL: vmovw dword ptr [rcx], xmm29
22+
0x62 0x65 0x7e 0x08 0x7e 0x29
23+
24+
# ATT: vmovw (%rcx), %xmm29
25+
# INTEL: vmovw xmm29, word ptr [rcx]
26+
0x62 0x65 0x7e 0x08 0x6e 0x29
27+
28+
# ATT: vmovw %xmm22, %xmm21
29+
# INTEL: vmovw xmm21, xmm22
30+
0x62 0xa5 0x7e 0x08 0x6e 0xee
31+
32+
# ATT: vmovw %xmm22, %xmm21
33+
# INTEL: vmovw xmm21, xmm22
34+
0x62 0xa5 0x7e 0x08 0x7e 0xee

‎llvm/test/MC/X86/avx10.2-copy-32-att.s

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,17 @@
1+
// RUN: llvm-mc -triple i386 --show-encoding %s | FileCheck %s
2+
3+
// CHECK: vmovd %xmm2, %xmm1
4+
// CHECK: encoding: [0x62,0xf1,0x7e,0x08,0x7e,0xca]
5+
vmovd %xmm2, %xmm1
6+
7+
// CHECK: vmovd %xmm2, %xmm1
8+
// CHECK: encoding: [0x62,0xf1,0x7d,0x08,0xd6,0xca]
9+
vmovd.s %xmm2, %xmm1
10+
11+
// CHECK: vmovw %xmm2, %xmm1
12+
// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x6e,0xca]
13+
vmovw %xmm2, %xmm1
14+
15+
// CHECK: vmovw %xmm2, %xmm1
16+
// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x7e,0xca]
17+
vmovw.s %xmm2, %xmm1

‎llvm/test/MC/X86/avx10.2-copy-32-intel.s

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,17 @@
1+
// RUN: llvm-mc -triple i386 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
2+
3+
// CHECK: vmovd xmm1, xmm2
4+
// CHECK: encoding: [0x62,0xf1,0x7e,0x08,0x7e,0xca]
5+
vmovd xmm1, xmm2
6+
7+
// CHECK: vmovd xmm1, xmm2
8+
// CHECK: encoding: [0x62,0xf1,0x7d,0x08,0xd6,0xca]
9+
vmovd.s xmm1, xmm2
10+
11+
// CHECK: vmovw xmm1, xmm2
12+
// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x6e,0xca]
13+
vmovw xmm1, xmm2
14+
15+
// CHECK: vmovw xmm1, xmm2
16+
// CHECK: encoding: [0x62,0xf5,0x7e,0x08,0x7e,0xca]
17+
vmovw.s xmm1, xmm2

‎llvm/test/MC/X86/avx10.2-copy-64-att.s

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,17 @@
1+
// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
2+
3+
// CHECK: vmovd %xmm22, %xmm21
4+
// CHECK: encoding: [0x62,0xa1,0x7e,0x08,0x7e,0xee]
5+
vmovd %xmm22, %xmm21
6+
7+
// CHECK: vmovd %xmm22, %xmm21
8+
// CHECK: encoding: [0x62,0xa1,0x7d,0x08,0xd6,0xee]
9+
vmovd.s %xmm22, %xmm21
10+
11+
// CHECK: vmovw %xmm22, %xmm21
12+
// CHECK: encoding: [0x62,0xa5,0x7e,0x08,0x6e,0xee]
13+
vmovw %xmm22, %xmm21
14+
15+
// CHECK: vmovw %xmm22, %xmm21
16+
// CHECK: encoding: [0x62,0xa5,0x7e,0x08,0x7e,0xee]
17+
vmovw.s %xmm22, %xmm21

‎llvm/test/MC/X86/avx10.2-copy-64-intel.s

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,17 @@
1+
// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
2+
3+
// CHECK: vmovd xmm21, xmm22
4+
// CHECK: encoding: [0x62,0xa1,0x7e,0x08,0x7e,0xee]
5+
vmovd xmm21, xmm22
6+
7+
// CHECK: vmovd xmm21, xmm22
8+
// CHECK: encoding: [0x62,0xa1,0x7d,0x08,0xd6,0xee]
9+
vmovd.s xmm21, xmm22
10+
11+
// CHECK: vmovw xmm21, xmm22
12+
// CHECK: encoding: [0x62,0xa5,0x7e,0x08,0x6e,0xee]
13+
vmovw xmm21, xmm22
14+
15+
// CHECK: vmovw xmm21, xmm22
16+
// CHECK: encoding: [0x62,0xa5,0x7e,0x08,0x7e,0xee]
17+
vmovw.s xmm21, xmm22

‎llvm/test/TableGen/x86-fold-tables.inc

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1614,8 +1614,10 @@ static const X86FoldTableEntry Table1[] = {
16141614
{X86::VMOVUPSZrr, X86::VMOVUPSZrm, 0},
16151615
{X86::VMOVUPSrr, X86::VMOVUPSrm, 0},
16161616
{X86::VMOVW2SHrr, X86::VMOVWrm, TB_NO_REVERSE},
1617+
{X86::VMOVZPDILo2PDIZrr, X86::VMOVZPDILo2PDIZrm, TB_NO_REVERSE},
16171618
{X86::VMOVZPQILo2PQIZrr, X86::VMOVQI2PQIZrm, TB_NO_REVERSE},
16181619
{X86::VMOVZPQILo2PQIrr, X86::VMOVQI2PQIrm, TB_NO_REVERSE},
1620+
{X86::VMOVZPWILo2PWIZrr, X86::VMOVZPWILo2PWIZrm, TB_NO_REVERSE},
16191621
{X86::VPABSBYrr, X86::VPABSBYrm, 0},
16201622
{X86::VPABSBZ128rr, X86::VPABSBZ128rm, 0},
16211623
{X86::VPABSBZ256rr, X86::VPABSBZ256rm, 0},

‎llvm/utils/TableGen/X86ManualInstrMapping.def

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,7 @@ NOCOMP(VPSRAQZ128ri)
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NOCOMP(VPSRAQZ128rm)
3333
NOCOMP(VPSRAQZ128rr)
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NOCOMP(VSCALEFPSZ128rm)
35+
NOCOMP(VMOVZPDILo2PDIZrr)
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NOCOMP(VDBPSADBWZ256rmi)
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NOCOMP(VDBPSADBWZ256rri)
3738
NOCOMP(VPMAXSQZ256rm)

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