Skip to content

Commit d0a39e6

Browse files
BeMgBeMg
authored
[RISCV] default enable splitting regalloc between RVV and other (#72950)
This patch make riscv-split-regalloc as true by default. It will not affect the codegen result if it vector register allocation doesn't exist. If there is the vector register allocation, it may affect the non-rvv register LiveInterval's segment/weight. It will make the allocation in a different order.
1 parent ca66df3 commit d0a39e6

File tree

7 files changed

+70
-66
lines changed

7 files changed

+70
-66
lines changed

‎llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -93,7 +93,7 @@ static cl::opt<bool>
9393
static cl::opt<bool>
9494
EnableSplitRegAlloc("riscv-split-regalloc", cl::Hidden,
9595
cl::desc("Enable Split RegisterAlloc for RVV"),
96-
cl::init(false));
96+
cl::init(true));
9797

9898
static cl::opt<bool> EnableMISchedLoadClustering(
9999
"riscv-misched-load-clustering", cl::Hidden,

‎llvm/test/CodeGen/RISCV/O0-pipeline.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,7 @@
4747
; CHECK-NEXT: Eliminate PHI nodes for register allocation
4848
; CHECK-NEXT: Two-Address instruction pass
4949
; CHECK-NEXT: Fast Register Allocator
50+
; CHECK-NEXT: Fast Register Allocator
5051
; CHECK-NEXT: Remove Redundant DEBUG_VALUE analysis
5152
; CHECK-NEXT: Fixup Statepoint Caller Saved
5253
; CHECK-NEXT: Lazy Machine Block Frequency Analysis

‎llvm/test/CodeGen/RISCV/O3-pipeline.ll

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -142,6 +142,10 @@
142142
; CHECK-NEXT: Machine Optimization Remark Emitter
143143
; CHECK-NEXT: Greedy Register Allocator
144144
; CHECK-NEXT: Virtual Register Rewriter
145+
; CHECK-NEXT: Virtual Register Map
146+
; CHECK-NEXT: Live Register Matrix
147+
; CHECK-NEXT: Greedy Register Allocator
148+
; CHECK-NEXT: Virtual Register Rewriter
145149
; CHECK-NEXT: Register Allocation Pass Scoring
146150
; CHECK-NEXT: Stack Slot Coloring
147151
; CHECK-NEXT: Machine Copy Propagation Pass

‎llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -3062,24 +3062,24 @@ define <vscale x 64 x i16> @vp_bitreverse_nxv64i16(<vscale x 64 x i16> %va, <vsc
30623062
; CHECK-NEXT: add a1, sp, a1
30633063
; CHECK-NEXT: addi a1, a1, 16
30643064
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
3065-
; CHECK-NEXT: csrr a1, vlenb
3066-
; CHECK-NEXT: srli a2, a1, 1
3065+
; CHECK-NEXT: csrr a2, vlenb
3066+
; CHECK-NEXT: srli a1, a2, 1
30673067
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
3068-
; CHECK-NEXT: vslidedown.vx v0, v0, a2
3069-
; CHECK-NEXT: slli a1, a1, 2
3070-
; CHECK-NEXT: sub a2, a0, a1
3071-
; CHECK-NEXT: sltu a3, a0, a2
3068+
; CHECK-NEXT: vslidedown.vx v0, v0, a1
3069+
; CHECK-NEXT: slli a2, a2, 2
3070+
; CHECK-NEXT: sub a1, a0, a2
3071+
; CHECK-NEXT: sltu a3, a0, a1
30723072
; CHECK-NEXT: addi a3, a3, -1
3073-
; CHECK-NEXT: and a2, a3, a2
3074-
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
3073+
; CHECK-NEXT: and a1, a3, a1
3074+
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
30753075
; CHECK-NEXT: vsrl.vi v8, v16, 8, v0.t
30763076
; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t
30773077
; CHECK-NEXT: vor.vv v16, v16, v8, v0.t
30783078
; CHECK-NEXT: vsrl.vi v8, v16, 4, v0.t
3079-
; CHECK-NEXT: lui a2, 1
3080-
; CHECK-NEXT: addi a2, a2, -241
3081-
; CHECK-NEXT: vand.vx v8, v8, a2, v0.t
3082-
; CHECK-NEXT: vand.vx v16, v16, a2, v0.t
3079+
; CHECK-NEXT: lui a1, 1
3080+
; CHECK-NEXT: addi a1, a1, -241
3081+
; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
3082+
; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
30833083
; CHECK-NEXT: vsll.vi v16, v16, 4, v0.t
30843084
; CHECK-NEXT: vor.vv v16, v8, v16, v0.t
30853085
; CHECK-NEXT: vsrl.vi v8, v16, 2, v0.t
@@ -3098,9 +3098,9 @@ define <vscale x 64 x i16> @vp_bitreverse_nxv64i16(<vscale x 64 x i16> %va, <vsc
30983098
; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
30993099
; CHECK-NEXT: addi a5, sp, 16
31003100
; CHECK-NEXT: vs8r.v v8, (a5) # Unknown-size Folded Spill
3101-
; CHECK-NEXT: bltu a0, a1, .LBB46_2
3101+
; CHECK-NEXT: bltu a0, a2, .LBB46_2
31023102
; CHECK-NEXT: # %bb.1:
3103-
; CHECK-NEXT: mv a0, a1
3103+
; CHECK-NEXT: mv a0, a2
31043104
; CHECK-NEXT: .LBB46_2:
31053105
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
31063106
; CHECK-NEXT: vmv1r.v v0, v24
@@ -3113,8 +3113,8 @@ define <vscale x 64 x i16> @vp_bitreverse_nxv64i16(<vscale x 64 x i16> %va, <vsc
31133113
; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
31143114
; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
31153115
; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t
3116-
; CHECK-NEXT: vand.vx v16, v16, a2, v0.t
3117-
; CHECK-NEXT: vand.vx v8, v8, a2, v0.t
3116+
; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
3117+
; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
31183118
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
31193119
; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
31203120
; CHECK-NEXT: vsrl.vi v16, v8, 2, v0.t

‎llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll

Lines changed: 44 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -976,24 +976,24 @@ define <vscale x 16 x i64> @fshr_v16i64(<vscale x 16 x i64> %a, <vscale x 16 x i
976976
; CHECK-NEXT: add a1, sp, a1
977977
; CHECK-NEXT: addi a1, a1, 16
978978
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
979-
; CHECK-NEXT: csrr a1, vlenb
980-
; CHECK-NEXT: slli a3, a1, 3
981-
; CHECK-NEXT: add a5, a0, a3
979+
; CHECK-NEXT: csrr a3, vlenb
980+
; CHECK-NEXT: slli a1, a3, 3
981+
; CHECK-NEXT: add a5, a0, a1
982982
; CHECK-NEXT: vl8re64.v v8, (a5)
983983
; CHECK-NEXT: csrr a5, vlenb
984984
; CHECK-NEXT: slli a5, a5, 3
985985
; CHECK-NEXT: add a5, sp, a5
986986
; CHECK-NEXT: addi a5, a5, 16
987987
; CHECK-NEXT: vs8r.v v8, (a5) # Unknown-size Folded Spill
988-
; CHECK-NEXT: srli a5, a1, 3
988+
; CHECK-NEXT: srli a5, a3, 3
989989
; CHECK-NEXT: vsetvli a6, zero, e8, mf4, ta, ma
990990
; CHECK-NEXT: vslidedown.vx v0, v0, a5
991-
; CHECK-NEXT: add a5, a2, a3
992-
; CHECK-NEXT: sub a3, a4, a1
993-
; CHECK-NEXT: sltu a6, a4, a3
991+
; CHECK-NEXT: add a5, a2, a1
992+
; CHECK-NEXT: sub a1, a4, a3
993+
; CHECK-NEXT: sltu a6, a4, a1
994994
; CHECK-NEXT: addi a6, a6, -1
995-
; CHECK-NEXT: and a6, a6, a3
996-
; CHECK-NEXT: li a3, 63
995+
; CHECK-NEXT: and a6, a6, a1
996+
; CHECK-NEXT: li a1, 63
997997
; CHECK-NEXT: vl8re64.v v8, (a5)
998998
; CHECK-NEXT: csrr a5, vlenb
999999
; CHECK-NEXT: li a7, 40
@@ -1021,7 +1021,7 @@ define <vscale x 16 x i64> @fshr_v16i64(<vscale x 16 x i64> %a, <vscale x 16 x i
10211021
; CHECK-NEXT: add a0, sp, a0
10221022
; CHECK-NEXT: addi a0, a0, 16
10231023
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
1024-
; CHECK-NEXT: vand.vx v8, v8, a3, v0.t
1024+
; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
10251025
; CHECK-NEXT: addi a0, sp, 16
10261026
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
10271027
; CHECK-NEXT: csrr a0, vlenb
@@ -1044,7 +1044,7 @@ define <vscale x 16 x i64> @fshr_v16i64(<vscale x 16 x i64> %a, <vscale x 16 x i
10441044
; CHECK-NEXT: addi a0, a0, 16
10451045
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
10461046
; CHECK-NEXT: vnot.v v8, v8, v0.t
1047-
; CHECK-NEXT: vand.vx v16, v8, a3, v0.t
1047+
; CHECK-NEXT: vand.vx v16, v8, a1, v0.t
10481048
; CHECK-NEXT: csrr a0, vlenb
10491049
; CHECK-NEXT: li a2, 24
10501050
; CHECK-NEXT: mul a0, a0, a2
@@ -1065,22 +1065,22 @@ define <vscale x 16 x i64> @fshr_v16i64(<vscale x 16 x i64> %a, <vscale x 16 x i
10651065
; CHECK-NEXT: add a0, sp, a0
10661066
; CHECK-NEXT: addi a0, a0, 16
10671067
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
1068-
; CHECK-NEXT: bltu a4, a1, .LBB46_2
1068+
; CHECK-NEXT: bltu a4, a3, .LBB46_2
10691069
; CHECK-NEXT: # %bb.1:
1070-
; CHECK-NEXT: mv a4, a1
1070+
; CHECK-NEXT: mv a4, a3
10711071
; CHECK-NEXT: .LBB46_2:
10721072
; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
10731073
; CHECK-NEXT: vmv1r.v v0, v24
10741074
; CHECK-NEXT: csrr a0, vlenb
1075-
; CHECK-NEXT: li a1, 48
1076-
; CHECK-NEXT: mul a0, a0, a1
1075+
; CHECK-NEXT: li a2, 48
1076+
; CHECK-NEXT: mul a0, a0, a2
10771077
; CHECK-NEXT: add a0, sp, a0
10781078
; CHECK-NEXT: addi a0, a0, 16
10791079
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
1080-
; CHECK-NEXT: vand.vx v8, v8, a3, v0.t
1080+
; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
10811081
; CHECK-NEXT: csrr a0, vlenb
1082-
; CHECK-NEXT: li a1, 24
1083-
; CHECK-NEXT: mul a0, a0, a1
1082+
; CHECK-NEXT: li a2, 24
1083+
; CHECK-NEXT: mul a0, a0, a2
10841084
; CHECK-NEXT: add a0, sp, a0
10851085
; CHECK-NEXT: addi a0, a0, 16
10861086
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
@@ -1090,26 +1090,26 @@ define <vscale x 16 x i64> @fshr_v16i64(<vscale x 16 x i64> %a, <vscale x 16 x i
10901090
; CHECK-NEXT: addi a0, a0, 16
10911091
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
10921092
; CHECK-NEXT: csrr a0, vlenb
1093-
; CHECK-NEXT: li a1, 24
1094-
; CHECK-NEXT: mul a0, a0, a1
1093+
; CHECK-NEXT: li a2, 24
1094+
; CHECK-NEXT: mul a0, a0, a2
10951095
; CHECK-NEXT: add a0, sp, a0
10961096
; CHECK-NEXT: addi a0, a0, 16
10971097
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
10981098
; CHECK-NEXT: vsrl.vv v8, v8, v16, v0.t
10991099
; CHECK-NEXT: csrr a0, vlenb
1100-
; CHECK-NEXT: li a1, 24
1101-
; CHECK-NEXT: mul a0, a0, a1
1100+
; CHECK-NEXT: li a2, 24
1101+
; CHECK-NEXT: mul a0, a0, a2
11021102
; CHECK-NEXT: add a0, sp, a0
11031103
; CHECK-NEXT: addi a0, a0, 16
11041104
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
11051105
; CHECK-NEXT: csrr a0, vlenb
1106-
; CHECK-NEXT: li a1, 48
1107-
; CHECK-NEXT: mul a0, a0, a1
1106+
; CHECK-NEXT: li a2, 48
1107+
; CHECK-NEXT: mul a0, a0, a2
11081108
; CHECK-NEXT: add a0, sp, a0
11091109
; CHECK-NEXT: addi a0, a0, 16
11101110
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
11111111
; CHECK-NEXT: vnot.v v16, v8, v0.t
1112-
; CHECK-NEXT: vand.vx v16, v16, a3, v0.t
1112+
; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
11131113
; CHECK-NEXT: csrr a0, vlenb
11141114
; CHECK-NEXT: slli a0, a0, 5
11151115
; CHECK-NEXT: add a0, sp, a0
@@ -1162,24 +1162,24 @@ define <vscale x 16 x i64> @fshl_v16i64(<vscale x 16 x i64> %a, <vscale x 16 x i
11621162
; CHECK-NEXT: add a1, sp, a1
11631163
; CHECK-NEXT: addi a1, a1, 16
11641164
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
1165-
; CHECK-NEXT: csrr a1, vlenb
1166-
; CHECK-NEXT: slli a3, a1, 3
1167-
; CHECK-NEXT: add a5, a0, a3
1165+
; CHECK-NEXT: csrr a3, vlenb
1166+
; CHECK-NEXT: slli a1, a3, 3
1167+
; CHECK-NEXT: add a5, a0, a1
11681168
; CHECK-NEXT: vl8re64.v v8, (a5)
11691169
; CHECK-NEXT: csrr a5, vlenb
11701170
; CHECK-NEXT: slli a5, a5, 4
11711171
; CHECK-NEXT: add a5, sp, a5
11721172
; CHECK-NEXT: addi a5, a5, 16
11731173
; CHECK-NEXT: vs8r.v v8, (a5) # Unknown-size Folded Spill
1174-
; CHECK-NEXT: srli a5, a1, 3
1174+
; CHECK-NEXT: srli a5, a3, 3
11751175
; CHECK-NEXT: vsetvli a6, zero, e8, mf4, ta, ma
11761176
; CHECK-NEXT: vslidedown.vx v0, v0, a5
1177-
; CHECK-NEXT: add a5, a2, a3
1178-
; CHECK-NEXT: sub a3, a4, a1
1179-
; CHECK-NEXT: sltu a6, a4, a3
1177+
; CHECK-NEXT: add a5, a2, a1
1178+
; CHECK-NEXT: sub a1, a4, a3
1179+
; CHECK-NEXT: sltu a6, a4, a1
11801180
; CHECK-NEXT: addi a6, a6, -1
1181-
; CHECK-NEXT: and a6, a6, a3
1182-
; CHECK-NEXT: li a3, 63
1181+
; CHECK-NEXT: and a6, a6, a1
1182+
; CHECK-NEXT: li a1, 63
11831183
; CHECK-NEXT: vl8re64.v v8, (a5)
11841184
; CHECK-NEXT: csrr a5, vlenb
11851185
; CHECK-NEXT: li a7, 40
@@ -1208,7 +1208,7 @@ define <vscale x 16 x i64> @fshl_v16i64(<vscale x 16 x i64> %a, <vscale x 16 x i
12081208
; CHECK-NEXT: add a0, sp, a0
12091209
; CHECK-NEXT: addi a0, a0, 16
12101210
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
1211-
; CHECK-NEXT: vand.vx v8, v8, a3, v0.t
1211+
; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
12121212
; CHECK-NEXT: addi a0, sp, 16
12131213
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
12141214
; CHECK-NEXT: csrr a0, vlenb
@@ -1231,7 +1231,7 @@ define <vscale x 16 x i64> @fshl_v16i64(<vscale x 16 x i64> %a, <vscale x 16 x i
12311231
; CHECK-NEXT: addi a0, a0, 16
12321232
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
12331233
; CHECK-NEXT: vnot.v v8, v8, v0.t
1234-
; CHECK-NEXT: vand.vx v16, v8, a3, v0.t
1234+
; CHECK-NEXT: vand.vx v16, v8, a1, v0.t
12351235
; CHECK-NEXT: csrr a0, vlenb
12361236
; CHECK-NEXT: slli a0, a0, 4
12371237
; CHECK-NEXT: add a0, sp, a0
@@ -1251,19 +1251,19 @@ define <vscale x 16 x i64> @fshl_v16i64(<vscale x 16 x i64> %a, <vscale x 16 x i
12511251
; CHECK-NEXT: add a0, sp, a0
12521252
; CHECK-NEXT: addi a0, a0, 16
12531253
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
1254-
; CHECK-NEXT: bltu a4, a1, .LBB47_2
1254+
; CHECK-NEXT: bltu a4, a3, .LBB47_2
12551255
; CHECK-NEXT: # %bb.1:
1256-
; CHECK-NEXT: mv a4, a1
1256+
; CHECK-NEXT: mv a4, a3
12571257
; CHECK-NEXT: .LBB47_2:
12581258
; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
12591259
; CHECK-NEXT: vmv1r.v v0, v24
12601260
; CHECK-NEXT: csrr a0, vlenb
1261-
; CHECK-NEXT: li a1, 48
1262-
; CHECK-NEXT: mul a0, a0, a1
1261+
; CHECK-NEXT: li a2, 48
1262+
; CHECK-NEXT: mul a0, a0, a2
12631263
; CHECK-NEXT: add a0, sp, a0
12641264
; CHECK-NEXT: addi a0, a0, 16
12651265
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
1266-
; CHECK-NEXT: vand.vx v8, v8, a3, v0.t
1266+
; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
12671267
; CHECK-NEXT: csrr a0, vlenb
12681268
; CHECK-NEXT: slli a0, a0, 4
12691269
; CHECK-NEXT: add a0, sp, a0
@@ -1286,13 +1286,13 @@ define <vscale x 16 x i64> @fshl_v16i64(<vscale x 16 x i64> %a, <vscale x 16 x i
12861286
; CHECK-NEXT: addi a0, a0, 16
12871287
; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
12881288
; CHECK-NEXT: csrr a0, vlenb
1289-
; CHECK-NEXT: li a1, 48
1290-
; CHECK-NEXT: mul a0, a0, a1
1289+
; CHECK-NEXT: li a2, 48
1290+
; CHECK-NEXT: mul a0, a0, a2
12911291
; CHECK-NEXT: add a0, sp, a0
12921292
; CHECK-NEXT: addi a0, a0, 16
12931293
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
12941294
; CHECK-NEXT: vnot.v v16, v8, v0.t
1295-
; CHECK-NEXT: vand.vx v16, v16, a3, v0.t
1295+
; CHECK-NEXT: vand.vx v16, v16, a1, v0.t
12961296
; CHECK-NEXT: csrr a0, vlenb
12971297
; CHECK-NEXT: li a1, 24
12981298
; CHECK-NEXT: mul a0, a0, a1

‎llvm/test/CodeGen/RISCV/rvv/regalloc-fast-crash.ll

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,6 @@ declare void @llvm.riscv.vsseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x
99
define void @test_vsseg2_mask_nxv16i16(<vscale x 16 x i16> %val, ptr %base, <vscale x 16 x i1> %mask, i32 %vl) {
1010
; CHECK-LABEL: test_vsseg2_mask_nxv16i16:
1111
; CHECK: # %bb.0: # %entry
12-
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
1312
; CHECK-NEXT: vmv4r.v v12, v8
1413
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
1514
; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t

‎llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3512,7 +3512,7 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
35123512
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
35133513
; CHECK-NEXT: csrr a3, vlenb
35143514
; CHECK-NEXT: li a1, 24
3515-
; CHECK-NEXT: mul t0, a3, a1
3515+
; CHECK-NEXT: mul t2, a3, a1
35163516
; CHECK-NEXT: slli t1, a3, 3
35173517
; CHECK-NEXT: srli a4, a3, 2
35183518
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
@@ -3521,17 +3521,17 @@ define <vscale x 32 x i1> @fcmp_oeq_vv_nxv32f64(<vscale x 32 x double> %va, <vsc
35213521
; CHECK-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
35223522
; CHECK-NEXT: add a5, a2, t1
35233523
; CHECK-NEXT: vl8re64.v v8, (a5)
3524-
; CHECK-NEXT: slli t3, a3, 4
3524+
; CHECK-NEXT: slli t0, a3, 4
35253525
; CHECK-NEXT: slli a5, a3, 1
35263526
; CHECK-NEXT: vslidedown.vx v0, v0, a1
35273527
; CHECK-NEXT: mv a7, a6
35283528
; CHECK-NEXT: bltu a6, a5, .LBB171_2
35293529
; CHECK-NEXT: # %bb.1:
35303530
; CHECK-NEXT: mv a7, a5
35313531
; CHECK-NEXT: .LBB171_2:
3532-
; CHECK-NEXT: add t2, a2, t0
3532+
; CHECK-NEXT: add t2, a2, t2
35333533
; CHECK-NEXT: add t1, a0, t1
3534-
; CHECK-NEXT: add t0, a2, t3
3534+
; CHECK-NEXT: add t0, a2, t0
35353535
; CHECK-NEXT: vl8re64.v v16, (a2)
35363536
; CHECK-NEXT: csrr a2, vlenb
35373537
; CHECK-NEXT: slli a2, a2, 4

0 commit comments

Comments
 (0)