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Krzysztof Parzyszek
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[Hexagon] Adding opExtentBits and opExtentAlign to GPrel instructions
Patch by Colin LeMahieu. llvm-svn: 293933
1 parent e6d59fd commit d0d42f0

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5 files changed

+66
-16
lines changed

5 files changed

+66
-16
lines changed

‎llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1756,8 +1756,8 @@ int HexagonAsmParser::processInstruction(MCInst &Inst,
17561756
TmpInst.setOpcode(Hexagon::L2_loadrdgp);
17571757

17581758
TmpInst.addOperand(MO_0);
1759-
TmpInst.addOperand(
1760-
MCOperand::createExpr(MCSymbolRefExpr::create(Sym, getContext())));
1759+
TmpInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create(
1760+
MCSymbolRefExpr::create(Sym, getContext()), getContext())));
17611761
Inst = TmpInst;
17621762
}
17631763
}

‎llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2543,6 +2543,14 @@ class T_StoreAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
25432543
!if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
25442544
!if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
25452545
/* u16_0Imm */ addr{15-0})));
2546+
let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
2547+
!if (!eq(ImmOpStr, "u16_2Imm"), 18,
2548+
!if (!eq(ImmOpStr, "u16_1Imm"), 17,
2549+
/* u16_0Imm */ 16)));
2550+
let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
2551+
!if (!eq(ImmOpStr, "u16_2Imm"), 2,
2552+
!if (!eq(ImmOpStr, "u16_1Imm"), 1,
2553+
/* u16_0Imm */ 0)));
25462554
// Store upper-half and store doubleword cannot be NV.
25472555
let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isHalf,0,1));
25482556
let Uses = !if (isAbs, [], [GP]);
@@ -2651,6 +2659,14 @@ class T_StoreAbsGP_NV <string mnemonic, Operand ImmOp, bits<2>MajOp>
26512659
!if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
26522660
!if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
26532661
/* u16_0Imm */ addr{15-0})));
2662+
let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
2663+
!if (!eq(ImmOpStr, "u16_2Imm"), 18,
2664+
!if (!eq(ImmOpStr, "u16_1Imm"), 17,
2665+
/* u16_0Imm */ 16)));
2666+
let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
2667+
!if (!eq(ImmOpStr, "u16_2Imm"), 2,
2668+
!if (!eq(ImmOpStr, "u16_1Imm"), 1,
2669+
/* u16_0Imm */ 0)));
26542670
let IClass = 0b0100;
26552671

26562672
let Inst{27} = 1;
@@ -2822,6 +2838,14 @@ class T_LoadAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
28222838
!if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2},
28232839
!if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1},
28242840
/* u16_0Imm */ addr{15-0})));
2841+
let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
2842+
!if (!eq(ImmOpStr, "u16_2Imm"), 18,
2843+
!if (!eq(ImmOpStr, "u16_1Imm"), 17,
2844+
/* u16_0Imm */ 16)));
2845+
let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3,
2846+
!if (!eq(ImmOpStr, "u16_2Imm"), 2,
2847+
!if (!eq(ImmOpStr, "u16_1Imm"), 1,
2848+
/* u16_0Imm */ 0)));
28252849

28262850
let IClass = 0b0100;
28272851

‎llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp

Lines changed: 25 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -521,7 +521,31 @@ unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI,
521521
if (HexagonMCInstrInfo::s23_2_reloc(*MO.getExpr()))
522522
FixupKind = Hexagon::fixup_Hexagon_23_REG;
523523
else
524-
raise_relocation_error(bits, kind);
524+
if (MCID.mayStore() || MCID.mayLoad()) {
525+
for (const MCPhysReg *ImpUses = MCID.getImplicitUses(); *ImpUses;
526+
++ImpUses) {
527+
if (*ImpUses != Hexagon::GP)
528+
continue;
529+
switch (HexagonMCInstrInfo::getAccessSize(MCII, MI)) {
530+
case HexagonII::MemAccessSize::ByteAccess:
531+
FixupKind = fixup_Hexagon_GPREL16_0;
532+
break;
533+
case HexagonII::MemAccessSize::HalfWordAccess:
534+
FixupKind = fixup_Hexagon_GPREL16_1;
535+
break;
536+
case HexagonII::MemAccessSize::WordAccess:
537+
FixupKind = fixup_Hexagon_GPREL16_2;
538+
break;
539+
case HexagonII::MemAccessSize::DoubleWordAccess:
540+
FixupKind = fixup_Hexagon_GPREL16_3;
541+
break;
542+
default:
543+
raise_relocation_error(bits, kind);
544+
}
545+
}
546+
}
547+
else
548+
raise_relocation_error(bits, kind);
525549
break;
526550
}
527551
case MCSymbolRefExpr::VK_DTPREL:

‎llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp

Lines changed: 11 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -707,6 +707,17 @@ bool HexagonMCInstrInfo::mustNotExtend(MCExpr const &Expr) {
707707
HexagonMCExpr const &HExpr = cast<HexagonMCExpr>(Expr);
708708
return HExpr.mustNotExtend();
709709
}
710+
void HexagonMCInstrInfo::setS23_2_reloc(MCExpr const &Expr, bool Val) {
711+
HexagonMCExpr &HExpr =
712+
const_cast<HexagonMCExpr &>(*llvm::cast<HexagonMCExpr>(&Expr));
713+
HExpr.setS23_2_reloc(Val);
714+
}
715+
bool HexagonMCInstrInfo::s23_2_reloc(MCExpr const &Expr) {
716+
HexagonMCExpr const *HExpr = llvm::dyn_cast<HexagonMCExpr>(&Expr);
717+
if (!HExpr)
718+
return false;
719+
return HExpr->s23_2_reloc();
720+
}
710721

711722
void HexagonMCInstrInfo::padEndloop(MCContext &Context, MCInst &MCB) {
712723
MCInst Nop;
@@ -772,15 +783,6 @@ void HexagonMCInstrInfo::setMemStoreReorderEnabled(MCInst &MCI) {
772783
Operand.setImm(Operand.getImm() | memStoreReorderEnabledMask);
773784
assert(isMemStoreReorderEnabled(MCI));
774785
}
775-
void HexagonMCInstrInfo::setS23_2_reloc(MCExpr const &Expr, bool Val) {
776-
HexagonMCExpr &HExpr =
777-
const_cast<HexagonMCExpr &>(*llvm::cast<HexagonMCExpr>(&Expr));
778-
HExpr.setS23_2_reloc(Val);
779-
}
780-
bool HexagonMCInstrInfo::s23_2_reloc(MCExpr const &Expr) {
781-
HexagonMCExpr const &HExpr = *llvm::cast<HexagonMCExpr>(&Expr);
782-
return HExpr.s23_2_reloc();
783-
}
784786

785787
void HexagonMCInstrInfo::setOuterLoop(MCInst &MCI) {
786788
assert(isBundle(MCI));

‎llvm/test/MC/Hexagon/relocations.s

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -30,19 +30,19 @@ r_hex_8:
3030

3131
# CHECK: R_HEX_GPREL16_0
3232
r_hex_gprel16_0:
33-
{ r0 = memb (#undefined@gotrel) }
33+
{ r0 = memb (gp+#undefined) }
3434

3535
# CHECK: R_HEX_GPREL16_1
3636
r_hex_gprel16_1:
37-
{ r0 = memh (#undefined@gotrel) }
37+
{ r0 = memh (gp+#undefined) }
3838

3939
# CHECK: R_HEX_GPREL16_2
4040
r_hex_gprel16_2:
41-
{ r0 = memw (#undefined@gotrel) }
41+
{ r0 = memw (gp+#undefined) }
4242

4343
# CHECK: R_HEX_GPREL16_3
4444
r_hex_gprel16_3:
45-
{ r1:0 = memd (#undefined@gotrel) }
45+
{ r1:0 = memd (gp+#undefined) }
4646

4747
# CHECK: R_HEX_B13_PCREL
4848
r_hex_b13_pcrel:

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