Skip to content

Commit d0f8047

Browse files
committed
[RISCV] Teach computeKnownBitsForTargetNode that VLENB will never be more than 65536/8.
1 parent f44fc35 commit d0f8047

File tree

2 files changed

+5
-3
lines changed

2 files changed

+5
-3
lines changed

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6452,6 +6452,8 @@ void RISCVTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
64526452
case RISCVISD::READ_VLENB:
64536453
// We assume VLENB is at least 16 bytes.
64546454
Known.Zero.setLowBits(4);
6455+
// We assume VLENB is no more than 65536 / 8 bytes.
6456+
Known.Zero.setBitsFrom(14);
64556457
break;
64566458
case ISD::INTRINSIC_W_CHAIN: {
64576459
unsigned IntNo = Op.getConstantOperandVal(1);

llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -50,9 +50,9 @@ define i64 @vscale_uimmpow2xlen() nounwind {
5050
;
5151
; RV32-LABEL: vscale_uimmpow2xlen:
5252
; RV32: # %bb.0: # %entry
53-
; RV32-NEXT: csrr a1, vlenb
54-
; RV32-NEXT: slli a0, a1, 3
55-
; RV32-NEXT: srli a1, a1, 29
53+
; RV32-NEXT: csrr a0, vlenb
54+
; RV32-NEXT: slli a0, a0, 3
55+
; RV32-NEXT: mv a1, zero
5656
; RV32-NEXT: ret
5757
entry:
5858
%0 = call i64 @llvm.vscale.i64()

0 commit comments

Comments
 (0)