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[RISCV] Use Sched*MC for Zvk MC instructions
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-11
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1 file changed

+13
-11
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llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td

Lines changed: 13 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -24,11 +24,9 @@ def tuimm5 : RISCVOp, TImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]>;
2424
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
2525
multiclass VCLMUL_MV_V_X<string opcodestr, bits<6> funct6> {
2626
def V : VALUVV<funct6, OPMVV, opcodestr # "." # "vv">,
27-
Sched<[WriteVIALUV_WorstCase, ReadVIALUV_WorstCase,
28-
ReadVIALUV_WorstCase, ReadVMask]>;
27+
SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
2928
def X : VALUVX<funct6, OPMVX, opcodestr # "." # "vx">,
30-
Sched<[WriteVIALUX_WorstCase, ReadVIALUV_WorstCase,
31-
ReadVIALUX_WorstCase, ReadVMask]>;
29+
SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
3230
}
3331

3432
class RVInstIVI_VROR<bits<6> funct6, dag outs, dag ins, string opcodestr,
@@ -57,29 +55,31 @@ multiclass VROR_IV_V_X_I<string opcodestr, bits<6> funct6>
5755
def I : RVInstIVI_VROR<funct6, (outs VR:$vd),
5856
(ins VR:$vs2, uimm6:$imm, VMaskOp:$vm),
5957
opcodestr # ".vi", "$vd, $vs2, $imm$vm">,
60-
Sched<[WriteVIALUI_WorstCase, ReadVIALUV_WorstCase,
61-
ReadVMask]>;
58+
SchedUnaryMC<"WriteVIALUI", "ReadVIALUV">;
6259
}
6360

6461
// op vd, vs2, vs1
6562
class PALUVVNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr>
66-
: VALUVVNoVm<funct6, opv, opcodestr> {
63+
: VALUVVNoVm<funct6, opv, opcodestr>,
64+
SchedUnaryMC<"WriteVIALUI", "ReadVIALUV"> {
6765
let Inst{6-0} = OPC_OP_VE.Value;
6866
}
6967

7068
// op vd, vs2, vs1
7169
class PALUVVNoVmTernary<bits<6> funct6, RISCVVFormat opv, string opcodestr>
7270
: RVInstVV<funct6, opv, (outs VR:$vd_wb),
7371
(ins VR:$vd, VR:$vs2, VR:$vs1),
74-
opcodestr, "$vd, $vs2, $vs1"> {
72+
opcodestr, "$vd, $vs2, $vs1">,
73+
SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV"> {
7574
let Constraints = "$vd = $vd_wb";
7675
let vm = 1;
7776
let Inst{6-0} = OPC_OP_VE.Value;
7877
}
7978

8079
// op vd, vs2, imm
8180
class PALUVINoVm<bits<6> funct6, string opcodestr, Operand optype>
82-
: VALUVINoVm<funct6, opcodestr, optype> {
81+
: VALUVINoVm<funct6, opcodestr, optype>,
82+
SchedUnaryMC<"WriteVIALUV", "ReadVIALUV"> {
8383
let Inst{6-0} = OPC_OP_VE.Value;
8484
let Inst{14-12} = OPMVV.Value;
8585
}
@@ -88,7 +88,8 @@ class PALUVINoVm<bits<6> funct6, string opcodestr, Operand optype>
8888
class PALUVINoVmBinary<bits<6> funct6, string opcodestr, Operand optype>
8989
: RVInstIVI<funct6, (outs VR:$vd_wb),
9090
(ins VR:$vd, VR:$vs2, optype:$imm),
91-
opcodestr, "$vd, $vs2, $imm"> {
91+
opcodestr, "$vd, $vs2, $imm">,
92+
SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV"> {
9293
let Constraints = "$vd = $vd_wb";
9394
let vm = 1;
9495
let Inst{6-0} = OPC_OP_VE.Value;
@@ -100,7 +101,8 @@ class PALUVINoVmBinary<bits<6> funct6, string opcodestr, Operand optype>
100101
class PALUVs2NoVmBinary<bits<6> funct6, bits<5> vs1, RISCVVFormat opv,
101102
string opcodestr>
102103
: RVInstV<funct6, vs1, opv, (outs VR:$vd_wb), (ins VR:$vd, VR:$vs2),
103-
opcodestr, "$vd, $vs2"> {
104+
opcodestr, "$vd, $vs2">,
105+
SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV"> {
104106
let Constraints = "$vd = $vd_wb";
105107
let vm = 1;
106108
let Inst{6-0} = OPC_OP_VE.Value;

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