Skip to content

Commit d1924f0

Browse files
author
Kai Luo
authored
[PowerPC] Do not generate isel instruction if target doesn't have this instruction (#72845)
When expand `select_cc` in finalize-isel, we should not generate `isel` for targets not feature it.
1 parent 1a2960b commit d1924f0

27 files changed

+1375
-1401
lines changed

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Lines changed: 51 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -12661,6 +12661,44 @@ PPCTargetLowering::emitProbedAlloca(MachineInstr &MI,
1266112661
return TailMBB;
1266212662
}
1266312663

12664+
static bool IsSelectCC(MachineInstr &MI) {
12665+
switch (MI.getOpcode()) {
12666+
case PPC::SELECT_CC_I4:
12667+
case PPC::SELECT_CC_I8:
12668+
case PPC::SELECT_CC_F4:
12669+
case PPC::SELECT_CC_F8:
12670+
case PPC::SELECT_CC_F16:
12671+
case PPC::SELECT_CC_VRRC:
12672+
case PPC::SELECT_CC_VSFRC:
12673+
case PPC::SELECT_CC_VSSRC:
12674+
case PPC::SELECT_CC_VSRC:
12675+
case PPC::SELECT_CC_SPE4:
12676+
case PPC::SELECT_CC_SPE:
12677+
return true;
12678+
default:
12679+
return false;
12680+
}
12681+
}
12682+
12683+
static bool IsSelect(MachineInstr &MI) {
12684+
switch (MI.getOpcode()) {
12685+
case PPC::SELECT_I4:
12686+
case PPC::SELECT_I8:
12687+
case PPC::SELECT_F4:
12688+
case PPC::SELECT_F8:
12689+
case PPC::SELECT_F16:
12690+
case PPC::SELECT_SPE:
12691+
case PPC::SELECT_SPE4:
12692+
case PPC::SELECT_VRRC:
12693+
case PPC::SELECT_VSFRC:
12694+
case PPC::SELECT_VSSRC:
12695+
case PPC::SELECT_VSRC:
12696+
return true;
12697+
default:
12698+
return false;
12699+
}
12700+
}
12701+
1266412702
MachineBasicBlock *
1266512703
PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1266612704
MachineBasicBlock *BB) const {
@@ -12698,9 +12736,10 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1269812736
MachineFunction *F = BB->getParent();
1269912737
MachineRegisterInfo &MRI = F->getRegInfo();
1270012738

12701-
if (MI.getOpcode() == PPC::SELECT_CC_I4 ||
12702-
MI.getOpcode() == PPC::SELECT_CC_I8 || MI.getOpcode() == PPC::SELECT_I4 ||
12703-
MI.getOpcode() == PPC::SELECT_I8) {
12739+
if (Subtarget.hasISEL() &&
12740+
(MI.getOpcode() == PPC::SELECT_CC_I4 ||
12741+
MI.getOpcode() == PPC::SELECT_CC_I8 ||
12742+
MI.getOpcode() == PPC::SELECT_I4 || MI.getOpcode() == PPC::SELECT_I8)) {
1270412743
SmallVector<MachineOperand, 2> Cond;
1270512744
if (MI.getOpcode() == PPC::SELECT_CC_I4 ||
1270612745
MI.getOpcode() == PPC::SELECT_CC_I8)
@@ -12712,24 +12751,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1271212751
DebugLoc dl = MI.getDebugLoc();
1271312752
TII->insertSelect(*BB, MI, dl, MI.getOperand(0).getReg(), Cond,
1271412753
MI.getOperand(2).getReg(), MI.getOperand(3).getReg());
12715-
} else if (MI.getOpcode() == PPC::SELECT_CC_F4 ||
12716-
MI.getOpcode() == PPC::SELECT_CC_F8 ||
12717-
MI.getOpcode() == PPC::SELECT_CC_F16 ||
12718-
MI.getOpcode() == PPC::SELECT_CC_VRRC ||
12719-
MI.getOpcode() == PPC::SELECT_CC_VSFRC ||
12720-
MI.getOpcode() == PPC::SELECT_CC_VSSRC ||
12721-
MI.getOpcode() == PPC::SELECT_CC_VSRC ||
12722-
MI.getOpcode() == PPC::SELECT_CC_SPE4 ||
12723-
MI.getOpcode() == PPC::SELECT_CC_SPE ||
12724-
MI.getOpcode() == PPC::SELECT_F4 ||
12725-
MI.getOpcode() == PPC::SELECT_F8 ||
12726-
MI.getOpcode() == PPC::SELECT_F16 ||
12727-
MI.getOpcode() == PPC::SELECT_SPE ||
12728-
MI.getOpcode() == PPC::SELECT_SPE4 ||
12729-
MI.getOpcode() == PPC::SELECT_VRRC ||
12730-
MI.getOpcode() == PPC::SELECT_VSFRC ||
12731-
MI.getOpcode() == PPC::SELECT_VSSRC ||
12732-
MI.getOpcode() == PPC::SELECT_VSRC) {
12754+
} else if (IsSelectCC(MI) || IsSelect(MI)) {
1273312755
// The incoming instruction knows the destination vreg to set, the
1273412756
// condition code register to branch on, the true/false values to
1273512757
// select between, and a branch opcode to use.
@@ -12738,7 +12760,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1273812760
// ...
1273912761
// TrueVal = ...
1274012762
// cmpTY ccX, r1, r2
12741-
// bCC copy1MBB
12763+
// bCC sinkMBB
1274212764
// fallthrough --> copy0MBB
1274312765
MachineBasicBlock *thisMBB = BB;
1274412766
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
@@ -12747,6 +12769,12 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1274712769
F->insert(It, copy0MBB);
1274812770
F->insert(It, sinkMBB);
1274912771

12772+
// Set the call frame size on entry to the new basic blocks.
12773+
// See https://reviews.llvm.org/D156113.
12774+
unsigned CallFrameSize = TII->getCallFrameSizeAt(MI);
12775+
copy0MBB->setCallFrameSize(CallFrameSize);
12776+
sinkMBB->setCallFrameSize(CallFrameSize);
12777+
1275012778
// Transfer the remainder of BB and its successor edges to sinkMBB.
1275112779
sinkMBB->splice(sinkMBB->begin(), BB,
1275212780
std::next(MachineBasicBlock::iterator(MI)), BB->end());
@@ -12756,15 +12784,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1275612784
BB->addSuccessor(copy0MBB);
1275712785
BB->addSuccessor(sinkMBB);
1275812786

12759-
if (MI.getOpcode() == PPC::SELECT_I4 || MI.getOpcode() == PPC::SELECT_I8 ||
12760-
MI.getOpcode() == PPC::SELECT_F4 || MI.getOpcode() == PPC::SELECT_F8 ||
12761-
MI.getOpcode() == PPC::SELECT_F16 ||
12762-
MI.getOpcode() == PPC::SELECT_SPE4 ||
12763-
MI.getOpcode() == PPC::SELECT_SPE ||
12764-
MI.getOpcode() == PPC::SELECT_VRRC ||
12765-
MI.getOpcode() == PPC::SELECT_VSFRC ||
12766-
MI.getOpcode() == PPC::SELECT_VSSRC ||
12767-
MI.getOpcode() == PPC::SELECT_VSRC) {
12787+
if (IsSelect(MI)) {
1276812788
BuildMI(BB, dl, TII->get(PPC::BC))
1276912789
.addReg(MI.getOperand(1).getReg())
1277012790
.addMBB(sinkMBB);

‎llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll

Lines changed: 31 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
3636
; CHECK-NEXT: # %bb.1: # %bb5
3737
; CHECK-NEXT: li 3, 0
3838
; CHECK-NEXT: li 4, 0
39-
; CHECK-NEXT: b .LBB0_17
39+
; CHECK-NEXT: b .LBB0_19
4040
; CHECK-NEXT: .LBB0_2: # %bb1
4141
; CHECK-NEXT: lfd 0, 400(1)
4242
; CHECK-NEXT: lis 3, 15856
@@ -99,24 +99,22 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
9999
; CHECK-NEXT: fadd 1, 28, 29
100100
; CHECK-NEXT: mtfsf 1, 0
101101
; CHECK-NEXT: lfs 0, .LCPI0_1@l(3)
102-
; CHECK-NEXT: fctiwz 1, 1
103-
; CHECK-NEXT: stfd 1, 152(1)
104102
; CHECK-NEXT: fcmpu 0, 28, 27
105-
; CHECK-NEXT: lwz 3, 164(1)
103+
; CHECK-NEXT: fctiwz 1, 1
106104
; CHECK-NEXT: fcmpu 1, 29, 0
107-
; CHECK-NEXT: lwz 4, 156(1)
108105
; CHECK-NEXT: crandc 20, 6, 0
109106
; CHECK-NEXT: cror 20, 5, 20
110-
; CHECK-NEXT: addis 3, 3, -32768
107+
; CHECK-NEXT: stfd 1, 152(1)
111108
; CHECK-NEXT: bc 12, 20, .LBB0_4
112109
; CHECK-NEXT: # %bb.3: # %bb1
113-
; CHECK-NEXT: ori 30, 4, 0
110+
; CHECK-NEXT: lwz 30, 156(1)
114111
; CHECK-NEXT: b .LBB0_5
115-
; CHECK-NEXT: .LBB0_4: # %bb1
116-
; CHECK-NEXT: addi 30, 3, 0
112+
; CHECK-NEXT: .LBB0_4:
113+
; CHECK-NEXT: lwz 3, 164(1)
114+
; CHECK-NEXT: addis 30, 3, -32768
117115
; CHECK-NEXT: .LBB0_5: # %bb1
118-
; CHECK-NEXT: li 4, 0
119116
; CHECK-NEXT: mr 3, 30
117+
; CHECK-NEXT: li 4, 0
120118
; CHECK-NEXT: bl __floatditf
121119
; CHECK-NEXT: lis 3, 17392
122120
; CHECK-NEXT: stfd 1, 208(1)
@@ -179,10 +177,10 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
179177
; CHECK-NEXT: lwz 3, 168(1)
180178
; CHECK-NEXT: stw 3, 272(1)
181179
; CHECK-NEXT: lfd 31, 272(1)
182-
; CHECK-NEXT: bc 12, 20, .LBB0_14
180+
; CHECK-NEXT: bc 12, 20, .LBB0_13
183181
; CHECK-NEXT: # %bb.10: # %bb1
184182
; CHECK-NEXT: cror 20, 1, 3
185-
; CHECK-NEXT: bc 12, 20, .LBB0_14
183+
; CHECK-NEXT: bc 12, 20, .LBB0_13
186184
; CHECK-NEXT: # %bb.11: # %bb2
187185
; CHECK-NEXT: fneg 29, 31
188186
; CHECK-NEXT: stfd 29, 48(1)
@@ -223,24 +221,17 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
223221
; CHECK-NEXT: fadd 1, 28, 29
224222
; CHECK-NEXT: mtfsf 1, 0
225223
; CHECK-NEXT: lfs 0, .LCPI0_3@l(3)
226-
; CHECK-NEXT: fctiwz 1, 1
227-
; CHECK-NEXT: stfd 1, 24(1)
228224
; CHECK-NEXT: fcmpu 0, 30, 2
229-
; CHECK-NEXT: lwz 3, 36(1)
225+
; CHECK-NEXT: fctiwz 1, 1
230226
; CHECK-NEXT: fcmpu 1, 31, 0
231-
; CHECK-NEXT: lwz 4, 28(1)
232227
; CHECK-NEXT: crandc 20, 6, 1
233228
; CHECK-NEXT: cror 20, 4, 20
234-
; CHECK-NEXT: addis 3, 3, -32768
235-
; CHECK-NEXT: bc 12, 20, .LBB0_13
229+
; CHECK-NEXT: stfd 1, 24(1)
230+
; CHECK-NEXT: bc 12, 20, .LBB0_17
236231
; CHECK-NEXT: # %bb.12: # %bb2
237-
; CHECK-NEXT: ori 3, 4, 0
238-
; CHECK-NEXT: b .LBB0_13
239-
; CHECK-NEXT: .LBB0_13: # %bb2
240-
; CHECK-NEXT: subfic 4, 3, 0
241-
; CHECK-NEXT: subfe 3, 29, 30
242-
; CHECK-NEXT: b .LBB0_17
243-
; CHECK-NEXT: .LBB0_14: # %bb3
232+
; CHECK-NEXT: lwz 3, 28(1)
233+
; CHECK-NEXT: b .LBB0_18
234+
; CHECK-NEXT: .LBB0_13: # %bb3
244235
; CHECK-NEXT: stfd 31, 112(1)
245236
; CHECK-NEXT: li 3, 0
246237
; CHECK-NEXT: stw 3, 148(1)
@@ -278,22 +269,29 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
278269
; CHECK-NEXT: fadd 2, 30, 31
279270
; CHECK-NEXT: mtfsf 1, 0
280271
; CHECK-NEXT: lfs 0, .LCPI0_1@l(3)
281-
; CHECK-NEXT: fctiwz 2, 2
282-
; CHECK-NEXT: stfd 2, 88(1)
283272
; CHECK-NEXT: fcmpu 0, 30, 1
284-
; CHECK-NEXT: lwz 3, 100(1)
273+
; CHECK-NEXT: fctiwz 1, 2
285274
; CHECK-NEXT: fcmpu 1, 31, 0
286-
; CHECK-NEXT: lwz 4, 92(1)
287275
; CHECK-NEXT: crandc 20, 6, 0
288276
; CHECK-NEXT: cror 20, 5, 20
289-
; CHECK-NEXT: addis 3, 3, -32768
277+
; CHECK-NEXT: stfd 1, 88(1)
290278
; CHECK-NEXT: bc 12, 20, .LBB0_15
279+
; CHECK-NEXT: # %bb.14: # %bb3
280+
; CHECK-NEXT: lwz 4, 92(1)
291281
; CHECK-NEXT: b .LBB0_16
292-
; CHECK-NEXT: .LBB0_15: # %bb3
293-
; CHECK-NEXT: addi 4, 3, 0
282+
; CHECK-NEXT: .LBB0_15:
283+
; CHECK-NEXT: lwz 3, 100(1)
284+
; CHECK-NEXT: addis 4, 3, -32768
294285
; CHECK-NEXT: .LBB0_16: # %bb3
295286
; CHECK-NEXT: mr 3, 30
296-
; CHECK-NEXT: .LBB0_17: # %bb5
287+
; CHECK-NEXT: b .LBB0_19
288+
; CHECK-NEXT: .LBB0_17:
289+
; CHECK-NEXT: lwz 3, 36(1)
290+
; CHECK-NEXT: addis 3, 3, -32768
291+
; CHECK-NEXT: .LBB0_18: # %bb2
292+
; CHECK-NEXT: subfic 4, 3, 0
293+
; CHECK-NEXT: subfe 3, 29, 30
294+
; CHECK-NEXT: .LBB0_19: # %bb3
297295
; CHECK-NEXT: lfd 31, 456(1) # 8-byte Folded Reload
298296
; CHECK-NEXT: lfd 30, 448(1) # 8-byte Folded Reload
299297
; CHECK-NEXT: lfd 29, 440(1) # 8-byte Folded Reload

0 commit comments

Comments
 (0)