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[RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (#68295)
SiFive Int8 Matrix Multiplication Extensions Specification https://sifive.cdn.prismic.io/sifive/c4f0e51d-4dd3-402a-98bc-1ffad6011259_int8-matmul-spec.pdf
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‎clang/include/clang/Basic/riscv_sifive_vector.td

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -103,3 +103,27 @@ let SupportOverloading = false in {
103103
defm sf_vc_v_fvw : RVVVCIXBuiltinSet<["si"], "UwKzUwUvFe", [-1, 0, 2, 3], UseGPR=0>;
104104
}
105105
}
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multiclass RVVVQMACCBuiltinSet<list<list<string>> suffixes_prototypes> {
108+
let OverloadedName = NAME,
109+
Name = NAME,
110+
HasMasked = false,
111+
Log2LMUL = [0, 1, 2, 3] in
112+
defm NAME : RVVOutOp1Op2BuiltinSet<NAME, "i", suffixes_prototypes>;
113+
}
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115+
let UnMaskedPolicyScheme = HasPolicyOperand in
116+
let RequiredFeatures = ["Xsfvqmaccdod"] in {
117+
defm sf_vqmaccu_2x8x2 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)SUv(FixedSEW:8)Uv"]]>;
118+
defm sf_vqmacc_2x8x2 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)Sv(FixedSEW:8)v"]]>;
119+
defm sf_vqmaccus_2x8x2 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)SUv(FixedSEW:8)v"]]>;
120+
defm sf_vqmaccsu_2x8x2 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)Sv(FixedSEW:8)Uv"]]>;
121+
}
122+
123+
let UnMaskedPolicyScheme = HasPolicyOperand in
124+
let RequiredFeatures = ["Xsfvqmaccqoq"] in {
125+
defm sf_vqmaccu_4x8x4 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)SUv(FixedSEW:8)Uv"]]>;
126+
defm sf_vqmacc_4x8x4 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)Sv(FixedSEW:8)v"]]>;
127+
defm sf_vqmaccus_4x8x4 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)SUv(FixedSEW:8)v"]]>;
128+
defm sf_vqmaccsu_4x8x4 : RVVVQMACCBuiltinSet<[["", "v", "vv(FixedSEW:8)Sv(FixedSEW:8)Uv"]]>;
129+
}

‎clang/include/clang/Support/RISCVVIntrinsicUtils.h

Lines changed: 10 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -485,14 +485,16 @@ enum RVVRequire : uint16_t {
485485
RVV_REQ_RV64 = 1 << 0,
486486
RVV_REQ_ZvfhminOrZvfh = 1 << 1,
487487
RVV_REQ_Xsfvcp = 1 << 2,
488-
RVV_REQ_Zvbb = 1 << 3,
489-
RVV_REQ_Zvbc = 1 << 4,
490-
RVV_REQ_Zvkb = 1 << 5,
491-
RVV_REQ_Zvkg = 1 << 6,
492-
RVV_REQ_Zvkned = 1 << 7,
493-
RVV_REQ_Zvknha = 1 << 8,
494-
RVV_REQ_Zvksed = 1 << 9,
495-
RVV_REQ_Zvksh = 1 << 10,
488+
RVV_REQ_Xsfvqmaccdod = 1 << 3,
489+
RVV_REQ_Xsfvqmaccqoq = 1 << 4,
490+
RVV_REQ_Zvbb = 1 << 5,
491+
RVV_REQ_Zvbc = 1 << 6,
492+
RVV_REQ_Zvkb = 1 << 7,
493+
RVV_REQ_Zvkg = 1 << 8,
494+
RVV_REQ_Zvkned = 1 << 9,
495+
RVV_REQ_Zvknha = 1 << 10,
496+
RVV_REQ_Zvksed = 1 << 11,
497+
RVV_REQ_Zvksh = 1 << 12,
496498

497499
LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Zvksh)
498500
};

‎clang/lib/Sema/SemaRISCVVectorLookup.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -205,6 +205,8 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
205205
static const std::pair<const char *, RVVRequire> FeatureCheckList[] = {
206206
{"64bit", RVV_REQ_RV64},
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{"xsfvcp", RVV_REQ_Xsfvcp},
208+
{"xsfvqmaccdod", RVV_REQ_Xsfvqmaccdod},
209+
{"xsfvqmaccqoq", RVV_REQ_Xsfvqmaccqoq},
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{"experimental-zvbb", RVV_REQ_Zvbb},
209211
{"experimental-zvbc", RVV_REQ_Zvbc},
210212
{"experimental-zvkb", RVV_REQ_Zvkb},

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmacc_2x8x2.c

Lines changed: 47 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,47 @@
1+
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
2+
// REQUIRES: riscv-registered-target
3+
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod \
4+
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \
5+
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
6+
7+
#include <sifive_vector.h>
8+
9+
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmacc_2x8x2_i32m1
10+
// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
11+
// CHECK-RV64-NEXT: entry:
12+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
13+
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
14+
//
15+
vint32m1_t test_sf_vqmacc_2x8x2_i32m1(vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {
16+
return __riscv_sf_vqmacc_2x8x2_i32m1(vd, vs1, vs2, vl);
17+
}
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// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmacc_2x8x2_i32m2
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// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
24+
//
25+
vint32m2_t test_sf_vqmacc_2x8x2_i32m2(vint32m2_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) {
26+
return __riscv_sf_vqmacc_2x8x2_i32m2(vd, vs1, vs2, vl);
27+
}
28+
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// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmacc_2x8x2_i32m4
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// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
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//
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vint32m4_t test_sf_vqmacc_2x8x2_i32m4(vint32m4_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) {
36+
return __riscv_sf_vqmacc_2x8x2_i32m4(vd, vs1, vs2, vl);
37+
}
38+
39+
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmacc_2x8x2_i32m8
40+
// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
41+
// CHECK-RV64-NEXT: entry:
42+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 3)
43+
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
44+
//
45+
vint32m8_t test_sf_vqmacc_2x8x2_i32m8(vint32m8_t vd, vint8m1_t vs1, vint8m8_t vs2, size_t vl) {
46+
return __riscv_sf_vqmacc_2x8x2_i32m8(vd, vs1, vs2, vl);
47+
}

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmacc_4x8x4.c

Lines changed: 47 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,47 @@
1+
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
2+
// REQUIRES: riscv-registered-target
3+
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq \
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// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \
5+
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
6+
7+
#include <sifive_vector.h>
8+
9+
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmacc_4x8x4_i32m1
10+
// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
11+
// CHECK-RV64-NEXT: entry:
12+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
13+
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
14+
//
15+
vint32m1_t test_sf_vqmacc_4x8x4_i32m1(vint32m1_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {
16+
return __riscv_sf_vqmacc_4x8x4_i32m1(vd, vs1, vs2, vl);
17+
}
18+
19+
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmacc_4x8x4_i32m2
20+
// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
21+
// CHECK-RV64-NEXT: entry:
22+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
23+
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
24+
//
25+
vint32m2_t test_sf_vqmacc_4x8x4_i32m2(vint32m2_t vd, vint8m1_t vs1, vint8m2_t vs2, size_t vl) {
26+
return __riscv_sf_vqmacc_4x8x4_i32m2(vd, vs1, vs2, vl);
27+
}
28+
29+
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmacc_4x8x4_i32m4
30+
// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
31+
// CHECK-RV64-NEXT: entry:
32+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
33+
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
34+
//
35+
vint32m4_t test_sf_vqmacc_4x8x4_i32m4(vint32m4_t vd, vint8m1_t vs1, vint8m4_t vs2, size_t vl) {
36+
return __riscv_sf_vqmacc_4x8x4_i32m4(vd, vs1, vs2, vl);
37+
}
38+
39+
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmacc_4x8x4_i32m8
40+
// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
41+
// CHECK-RV64-NEXT: entry:
42+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmacc.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 3)
43+
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
44+
//
45+
vint32m8_t test_sf_vqmacc_4x8x4_i32m8(vint32m8_t vd, vint8m1_t vs1, vint8m8_t vs2, size_t vl) {
46+
return __riscv_sf_vqmacc_4x8x4_i32m8(vd, vs1, vs2, vl);
47+
}

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccsu_2x8x2.c

Lines changed: 47 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,47 @@
1+
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
2+
// REQUIRES: riscv-registered-target
3+
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod \
4+
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \
5+
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
6+
7+
#include <sifive_vector.h>
8+
9+
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_2x8x2_i32m1
10+
// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
11+
// CHECK-RV64-NEXT: entry:
12+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
13+
// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
14+
//
15+
vint32m1_t test_sf_vqmaccsu_2x8x2_i32m1(vint32m1_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
16+
return __riscv_sf_vqmaccsu_2x8x2_i32m1(vd, vs1, vs2, vl);
17+
}
18+
19+
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_2x8x2_i32m2
20+
// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
21+
// CHECK-RV64-NEXT: entry:
22+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
23+
// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
24+
//
25+
vint32m2_t test_sf_vqmaccsu_2x8x2_i32m2(vint32m2_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
26+
return __riscv_sf_vqmaccsu_2x8x2_i32m2(vd, vs1, vs2, vl);
27+
}
28+
29+
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_2x8x2_i32m4
30+
// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
31+
// CHECK-RV64-NEXT: entry:
32+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
33+
// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
34+
//
35+
vint32m4_t test_sf_vqmaccsu_2x8x2_i32m4(vint32m4_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
36+
return __riscv_sf_vqmaccsu_2x8x2_i32m4(vd, vs1, vs2, vl);
37+
}
38+
39+
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_2x8x2_i32m8
40+
// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
41+
// CHECK-RV64-NEXT: entry:
42+
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 3)
43+
// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
44+
//
45+
vint32m8_t test_sf_vqmaccsu_2x8x2_i32m8(vint32m8_t vd, vint8m1_t vs1, vuint8m8_t vs2, size_t vl) {
46+
return __riscv_sf_vqmaccsu_2x8x2_i32m8(vd, vs1, vs2, vl);
47+
}

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccsu_4x8x4.c

Lines changed: 47 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,47 @@
1+
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
2+
// REQUIRES: riscv-registered-target
3+
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccqoq \
4+
// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \
5+
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
6+
7+
#include <sifive_vector.h>
8+
9+
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmaccsu_4x8x4_i32m1
10+
// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
11+
// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
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//
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vint32m1_t test_sf_vqmaccsu_4x8x4_i32m1(vint32m1_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
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return __riscv_sf_vqmaccsu_4x8x4_i32m1(vd, vs1, vs2, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmaccsu_4x8x4_i32m2
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// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
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//
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vint32m2_t test_sf_vqmaccsu_4x8x4_i32m2(vint32m2_t vd, vint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
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return __riscv_sf_vqmaccsu_4x8x4_i32m2(vd, vs1, vs2, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmaccsu_4x8x4_i32m4
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// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
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//
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vint32m4_t test_sf_vqmaccsu_4x8x4_i32m4(vint32m4_t vd, vint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
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return __riscv_sf_vqmaccsu_4x8x4_i32m4(vd, vs1, vs2, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmaccsu_4x8x4_i32m8
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// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccsu.4x8x4.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
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//
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vint32m8_t test_sf_vqmaccsu_4x8x4_i32m8(vint32m8_t vd, vint8m1_t vs1, vuint8m8_t vs2, size_t vl) {
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return __riscv_sf_vqmaccsu_4x8x4_i32m8(vd, vs1, vs2, vl);
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}

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/sf_vqmaccu_2x8x2.c

Lines changed: 47 additions & 0 deletions
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
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// REQUIRES: riscv-registered-target
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// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvqmaccdod \
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// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | \
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// RUN: FileCheck --check-prefix=CHECK-RV64 %s
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#include <sifive_vector.h>
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// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_sf_vqmaccu_2x8x2_i32m1
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// CHECK-RV64-SAME: (<vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 8 x i8> [[VS2]], i64 [[VL]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
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//
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vint32m1_t test_sf_vqmaccu_2x8x2_i32m1(vint32m1_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
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return __riscv_sf_vqmaccu_2x8x2_i32m1(vd, vs1, vs2, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_sf_vqmaccu_2x8x2_i32m2
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// CHECK-RV64-SAME: (<vscale x 4 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv4i32.nxv8i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 16 x i8> [[VS2]], i64 [[VL]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]]
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//
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vint32m2_t test_sf_vqmaccu_2x8x2_i32m2(vint32m2_t vd, vuint8m1_t vs1, vuint8m2_t vs2, size_t vl) {
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return __riscv_sf_vqmaccu_2x8x2_i32m2(vd, vs1, vs2, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_sf_vqmaccu_2x8x2_i32m4
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// CHECK-RV64-SAME: (<vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv8i32.nxv8i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 32 x i8> [[VS2]], i64 [[VL]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]]
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//
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vint32m4_t test_sf_vqmaccu_2x8x2_i32m4(vint32m4_t vd, vuint8m1_t vs1, vuint8m4_t vs2, size_t vl) {
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return __riscv_sf_vqmaccu_2x8x2_i32m4(vd, vs1, vs2, vl);
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}
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// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_sf_vqmaccu_2x8x2_i32m8
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// CHECK-RV64-SAME: (<vscale x 16 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS1:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
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// CHECK-RV64-NEXT: entry:
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// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.sf.vqmaccu.2x8x2.nxv16i32.nxv8i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 8 x i8> [[VS1]], <vscale x 64 x i8> [[VS2]], i64 [[VL]], i64 3)
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// CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]]
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//
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vint32m8_t test_sf_vqmaccu_2x8x2_i32m8(vint32m8_t vd, vuint8m1_t vs1, vuint8m8_t vs2, size_t vl) {
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return __riscv_sf_vqmaccu_2x8x2_i32m8(vd, vs1, vs2, vl);
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}

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