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‎llvm/test/CodeGen/AArch64/reduce-or-opt.ll

Lines changed: 195 additions & 0 deletions
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+sve | FileCheck %s
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define i64 @select_or_reduce_v2i1(ptr nocapture noundef readonly %src) {
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; CHECK-LABEL: select_or_reduce_v2i1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov x8, xzr
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; CHECK-NEXT: .LBB0_1: // %vector.body
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: ldr q0, [x0, x8]
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; CHECK-NEXT: cmeq v0.2d, v0.2d, #0
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; CHECK-NEXT: xtn v0.2s, v0.2d
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; CHECK-NEXT: umaxp v0.2s, v0.2s, v0.2s
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; CHECK-NEXT: fmov w9, s0
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; CHECK-NEXT: tbnz w9, #0, .LBB0_3
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; CHECK-NEXT: // %bb.2: // %vector.body
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; CHECK-NEXT: // in Loop: Header=BB0_1 Depth=1
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; CHECK-NEXT: cmp x8, #16
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; CHECK-NEXT: add x8, x8, #16
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; CHECK-NEXT: b.ne .LBB0_1
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; CHECK-NEXT: .LBB0_3: // %middle.split
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; CHECK-NEXT: and x0, x9, #0x1
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; CHECK-NEXT: ret
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entry:
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br label %vector.body
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vector.body:
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%index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
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%arrayidx = getelementptr inbounds ptr, ptr %src, i64 %index
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%wide.load = load <2 x ptr>, ptr %arrayidx, align 8
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%cond = icmp eq <2 x ptr> %wide.load, splat(ptr zeroinitializer)
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%index.next = add nuw i64 %index, 2
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%or.reduc = tail call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> %cond)
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%iv.cmp = icmp eq i64 %index.next, 4
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%exit.cond = or i1 %or.reduc, %iv.cmp
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br i1 %exit.cond, label %middle.split, label %vector.body
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middle.split:
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%sel = select i1 %or.reduc, i64 1, i64 0
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ret i64 %sel
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}
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define i64 @br_or_reduce_v2i1(ptr nocapture noundef readonly %src, ptr noundef readnone %p) {
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; CHECK-LABEL: br_or_reduce_v2i1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov x8, xzr
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; CHECK-NEXT: .LBB1_1: // %vector.body
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: ldr q0, [x0, x8]
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; CHECK-NEXT: cmeq v0.2d, v0.2d, #0
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; CHECK-NEXT: xtn v0.2s, v0.2d
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; CHECK-NEXT: umaxp v0.2s, v0.2s, v0.2s
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; CHECK-NEXT: fmov w9, s0
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; CHECK-NEXT: tbnz w9, #0, .LBB1_3
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; CHECK-NEXT: // %bb.2: // %vector.body
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; CHECK-NEXT: // in Loop: Header=BB1_1 Depth=1
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; CHECK-NEXT: cmp x8, #16
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; CHECK-NEXT: add x8, x8, #16
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; CHECK-NEXT: b.ne .LBB1_1
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; CHECK-NEXT: .LBB1_3: // %middle.split
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; CHECK-NEXT: tbz w9, #0, .LBB1_5
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; CHECK-NEXT: // %bb.4: // %found
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; CHECK-NEXT: mov w8, #56 // =0x38
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; CHECK-NEXT: mov w0, #1 // =0x1
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; CHECK-NEXT: str x8, [x1]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB1_5:
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; CHECK-NEXT: mov x0, xzr
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; CHECK-NEXT: ret
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entry:
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br label %vector.body
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vector.body:
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%index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
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%arrayidx = getelementptr inbounds ptr, ptr %src, i64 %index
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%wide.load = load <2 x ptr>, ptr %arrayidx, align 8
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%cond = icmp eq <2 x ptr> %wide.load, splat(ptr zeroinitializer)
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%index.next = add nuw i64 %index, 2
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%or.reduc = tail call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> %cond)
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%iv.cmp = icmp eq i64 %index.next, 4
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%exit.cond = or i1 %or.reduc, %iv.cmp
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br i1 %exit.cond, label %middle.split, label %vector.body
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middle.split:
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br i1 %or.reduc, label %found, label %notfound
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found:
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store i64 56, ptr %p, align 8
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ret i64 1
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notfound:
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ret i64 0
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}
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define i64 @select_or_reduce_nxv2i1(ptr nocapture noundef readonly %src) {
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; CHECK-LABEL: select_or_reduce_nxv2i1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cntd x9
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: mov x10, xzr
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; CHECK-NEXT: neg x8, x9
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; CHECK-NEXT: add x11, x8, #4
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; CHECK-NEXT: .LBB2_1: // %vector.body
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, x10, lsl #3]
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; CHECK-NEXT: cmpeq p1.d, p0/z, z0.d, #0
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; CHECK-NEXT: cset w8, ne
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; CHECK-NEXT: b.ne .LBB2_3
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; CHECK-NEXT: // %bb.2: // %vector.body
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; CHECK-NEXT: // in Loop: Header=BB2_1 Depth=1
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; CHECK-NEXT: cmp x11, x10
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; CHECK-NEXT: add x10, x10, x9
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; CHECK-NEXT: b.ne .LBB2_1
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; CHECK-NEXT: .LBB2_3: // %middle.split
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; CHECK-NEXT: mov x0, x8
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; CHECK-NEXT: ret
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entry:
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%vscale = tail call i64 @llvm.vscale.i64()
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%vf = shl nuw nsw i64 %vscale, 1
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br label %vector.body
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vector.body:
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%index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
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%arrayidx = getelementptr inbounds ptr, ptr %src, i64 %index
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%wide.load = load <vscale x 2 x ptr>, ptr %arrayidx, align 8
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%cond = icmp eq <vscale x 2 x ptr> %wide.load, splat(ptr zeroinitializer)
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%index.next = add nuw i64 %index, %vf
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%or.reduc = tail call i1 @llvm.vector.reduce.or.nxv2i1(<vscale x 2 x i1> %cond)
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%iv.cmp = icmp eq i64 %index.next, 4
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%exit.cond = or i1 %or.reduc, %iv.cmp
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br i1 %exit.cond, label %middle.split, label %vector.body
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middle.split:
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%sel = select i1 %or.reduc, i64 1, i64 0
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ret i64 %sel
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}
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define i64 @br_or_reduce_nxv2i1(ptr nocapture noundef readonly %src, ptr noundef readnone %p) {
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; CHECK-LABEL: br_or_reduce_nxv2i1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cntd x8
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: mov x9, xzr
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; CHECK-NEXT: neg x10, x8
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; CHECK-NEXT: add x10, x10, #4
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; CHECK-NEXT: .LBB3_1: // %vector.body
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0, x9, lsl #3]
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; CHECK-NEXT: cmpeq p1.d, p0/z, z0.d, #0
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; CHECK-NEXT: cset w11, ne
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; CHECK-NEXT: b.ne .LBB3_3
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; CHECK-NEXT: // %bb.2: // %vector.body
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; CHECK-NEXT: // in Loop: Header=BB3_1 Depth=1
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; CHECK-NEXT: cmp x10, x9
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; CHECK-NEXT: add x9, x9, x8
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; CHECK-NEXT: b.ne .LBB3_1
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; CHECK-NEXT: .LBB3_3: // %middle.split
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; CHECK-NEXT: tbz w11, #0, .LBB3_5
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; CHECK-NEXT: // %bb.4: // %found
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; CHECK-NEXT: mov w8, #56 // =0x38
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; CHECK-NEXT: mov w0, #1 // =0x1
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; CHECK-NEXT: str x8, [x1]
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB3_5:
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; CHECK-NEXT: mov x0, xzr
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; CHECK-NEXT: ret
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entry:
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%vscale = tail call i64 @llvm.vscale.i64()
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%vf = shl nuw nsw i64 %vscale, 1
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br label %vector.body
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vector.body:
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%index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
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%arrayidx = getelementptr inbounds ptr, ptr %src, i64 %index
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%wide.load = load <vscale x 2 x ptr>, ptr %arrayidx, align 8
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%cond = icmp eq <vscale x 2 x ptr> %wide.load, splat(ptr zeroinitializer)
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%index.next = add nuw i64 %index, %vf
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%or.reduc = tail call i1 @llvm.vector.reduce.or.nxv2i1(<vscale x 2 x i1> %cond)
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%iv.cmp = icmp eq i64 %index.next, 4
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%exit.cond = or i1 %or.reduc, %iv.cmp
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br i1 %exit.cond, label %middle.split, label %vector.body
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middle.split:
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br i1 %or.reduc, label %found, label %notfound
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found:
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store i64 56, ptr %p, align 8
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ret i64 1
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notfound:
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ret i64 0
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}
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declare i1 @llvm.vector.reduce.or.v2i1(<2 x i1>)
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declare i1 @llvm.vector.reduce.or.nxv2i1(<vscale x 2 x i1>)

‎llvm/test/Transforms/CodeGenPrepare/AArch64/reduce-or-opt.ll

Lines changed: 185 additions & 0 deletions
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -codegenprepare -S < %s -mtriple=aarch64-none-linux-gnu -mattr=+sve | FileCheck %s
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define i64 @select_or_reduce_v2i1(ptr nocapture noundef readonly %src) {
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; CHECK-LABEL: define i64 @select_or_reduce_v2i1(
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; CHECK-SAME: ptr nocapture noundef readonly [[SRC:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[SRC]], i64 [[INDEX]]
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; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x ptr>, ptr [[ARRAYIDX]], align 8
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; CHECK-NEXT: [[COND:%.*]] = icmp eq <2 x ptr> [[WIDE_LOAD]], zeroinitializer
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
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; CHECK-NEXT: [[OR_REDUC:%.*]] = tail call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> [[COND]])
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; CHECK-NEXT: [[IV_CMP:%.*]] = icmp eq i64 [[INDEX_NEXT]], 4
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; CHECK-NEXT: [[EXIT_COND:%.*]] = or i1 [[OR_REDUC]], [[IV_CMP]]
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; CHECK-NEXT: br i1 [[EXIT_COND]], label %[[MIDDLE_SPLIT:.*]], label %[[VECTOR_BODY]]
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; CHECK: [[MIDDLE_SPLIT]]:
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; CHECK-NEXT: [[SEL:%.*]] = select i1 [[OR_REDUC]], i64 1, i64 0
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; CHECK-NEXT: ret i64 [[SEL]]
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;
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entry:
24+
br label %vector.body
25+
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vector.body:
27+
%index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
28+
%arrayidx = getelementptr inbounds ptr, ptr %src, i64 %index
29+
%wide.load = load <2 x ptr>, ptr %arrayidx, align 8
30+
%cond = icmp eq <2 x ptr> %wide.load, splat(ptr zeroinitializer)
31+
%index.next = add nuw i64 %index, 2
32+
%or.reduc = tail call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> %cond)
33+
%iv.cmp = icmp eq i64 %index.next, 4
34+
%exit.cond = or i1 %or.reduc, %iv.cmp
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br i1 %exit.cond, label %middle.split, label %vector.body
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middle.split:
38+
%sel = select i1 %or.reduc, i64 1, i64 0
39+
ret i64 %sel
40+
}
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define i64 @br_or_reduce_v2i1(ptr nocapture noundef readonly %src, ptr noundef readnone %p) {
43+
; CHECK-LABEL: define i64 @br_or_reduce_v2i1(
44+
; CHECK-SAME: ptr nocapture noundef readonly [[SRC:%.*]], ptr noundef readnone [[P:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[ENTRY:.*]]:
46+
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
49+
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[SRC]], i64 [[INDEX]]
50+
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x ptr>, ptr [[ARRAYIDX]], align 8
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; CHECK-NEXT: [[COND:%.*]] = icmp eq <2 x ptr> [[WIDE_LOAD]], zeroinitializer
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
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; CHECK-NEXT: [[OR_REDUC:%.*]] = tail call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> [[COND]])
54+
; CHECK-NEXT: [[IV_CMP:%.*]] = icmp eq i64 [[INDEX_NEXT]], 4
55+
; CHECK-NEXT: [[EXIT_COND:%.*]] = or i1 [[OR_REDUC]], [[IV_CMP]]
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; CHECK-NEXT: br i1 [[EXIT_COND]], label %[[MIDDLE_SPLIT:.*]], label %[[VECTOR_BODY]]
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; CHECK: [[MIDDLE_SPLIT]]:
58+
; CHECK-NEXT: br i1 [[OR_REDUC]], label %[[FOUND:.*]], label %[[NOTFOUND:.*]]
59+
; CHECK: [[FOUND]]:
60+
; CHECK-NEXT: store i64 56, ptr [[P]], align 8
61+
; CHECK-NEXT: ret i64 1
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; CHECK: [[NOTFOUND]]:
63+
; CHECK-NEXT: ret i64 0
64+
;
65+
entry:
66+
br label %vector.body
67+
68+
vector.body:
69+
%index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
70+
%arrayidx = getelementptr inbounds ptr, ptr %src, i64 %index
71+
%wide.load = load <2 x ptr>, ptr %arrayidx, align 8
72+
%cond = icmp eq <2 x ptr> %wide.load, splat(ptr zeroinitializer)
73+
%index.next = add nuw i64 %index, 2
74+
%or.reduc = tail call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> %cond)
75+
%iv.cmp = icmp eq i64 %index.next, 4
76+
%exit.cond = or i1 %or.reduc, %iv.cmp
77+
br i1 %exit.cond, label %middle.split, label %vector.body
78+
79+
middle.split:
80+
br i1 %or.reduc, label %found, label %notfound
81+
82+
found:
83+
store i64 56, ptr %p, align 8
84+
ret i64 1
85+
86+
notfound:
87+
ret i64 0
88+
}
89+
90+
define i64 @select_or_reduce_nxv2i1(ptr nocapture noundef readonly %src) {
91+
; CHECK-LABEL: define i64 @select_or_reduce_nxv2i1(
92+
; CHECK-SAME: ptr nocapture noundef readonly [[SRC:%.*]]) #[[ATTR0]] {
93+
; CHECK-NEXT: [[ENTRY:.*]]:
94+
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
95+
; CHECK: [[VECTOR_BODY]]:
96+
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
97+
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[SRC]], i64 [[INDEX]]
98+
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x ptr>, ptr [[ARRAYIDX]], align 8
99+
; CHECK-NEXT: [[COND:%.*]] = icmp eq <vscale x 2 x ptr> [[WIDE_LOAD]], zeroinitializer
100+
; CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.vscale.i64()
101+
; CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i64 [[TMP0]], 1
102+
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]]
103+
; CHECK-NEXT: [[OR_REDUC:%.*]] = tail call i1 @llvm.vector.reduce.or.nxv2i1(<vscale x 2 x i1> [[COND]])
104+
; CHECK-NEXT: [[IV_CMP:%.*]] = icmp eq i64 [[INDEX_NEXT]], 4
105+
; CHECK-NEXT: [[EXIT_COND:%.*]] = or i1 [[OR_REDUC]], [[IV_CMP]]
106+
; CHECK-NEXT: br i1 [[EXIT_COND]], label %[[MIDDLE_SPLIT:.*]], label %[[VECTOR_BODY]]
107+
; CHECK: [[MIDDLE_SPLIT]]:
108+
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[OR_REDUC]], i64 1, i64 0
109+
; CHECK-NEXT: ret i64 [[SEL]]
110+
;
111+
entry:
112+
%vscale = tail call i64 @llvm.vscale.i64()
113+
%vf = shl nuw nsw i64 %vscale, 1
114+
br label %vector.body
115+
116+
vector.body:
117+
%index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
118+
%arrayidx = getelementptr inbounds ptr, ptr %src, i64 %index
119+
%wide.load = load <vscale x 2 x ptr>, ptr %arrayidx, align 8
120+
%cond = icmp eq <vscale x 2 x ptr> %wide.load, splat(ptr zeroinitializer)
121+
%index.next = add nuw i64 %index, %vf
122+
%or.reduc = tail call i1 @llvm.vector.reduce.or.nxv2i1(<vscale x 2 x i1> %cond)
123+
%iv.cmp = icmp eq i64 %index.next, 4
124+
%exit.cond = or i1 %or.reduc, %iv.cmp
125+
br i1 %exit.cond, label %middle.split, label %vector.body
126+
127+
middle.split:
128+
%sel = select i1 %or.reduc, i64 1, i64 0
129+
ret i64 %sel
130+
}
131+
132+
define i64 @br_or_reduce_nxv2i1(ptr nocapture noundef readonly %src, ptr noundef readnone %p) {
133+
; CHECK-LABEL: define i64 @br_or_reduce_nxv2i1(
134+
; CHECK-SAME: ptr nocapture noundef readonly [[SRC:%.*]], ptr noundef readnone [[P:%.*]]) #[[ATTR0]] {
135+
; CHECK-NEXT: [[ENTRY:.*]]:
136+
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
137+
; CHECK: [[VECTOR_BODY]]:
138+
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
139+
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[SRC]], i64 [[INDEX]]
140+
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x ptr>, ptr [[ARRAYIDX]], align 8
141+
; CHECK-NEXT: [[COND:%.*]] = icmp eq <vscale x 2 x ptr> [[WIDE_LOAD]], zeroinitializer
142+
; CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.vscale.i64()
143+
; CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i64 [[TMP0]], 1
144+
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]]
145+
; CHECK-NEXT: [[OR_REDUC:%.*]] = tail call i1 @llvm.vector.reduce.or.nxv2i1(<vscale x 2 x i1> [[COND]])
146+
; CHECK-NEXT: [[IV_CMP:%.*]] = icmp eq i64 [[INDEX_NEXT]], 4
147+
; CHECK-NEXT: [[EXIT_COND:%.*]] = or i1 [[OR_REDUC]], [[IV_CMP]]
148+
; CHECK-NEXT: br i1 [[EXIT_COND]], label %[[MIDDLE_SPLIT:.*]], label %[[VECTOR_BODY]]
149+
; CHECK: [[MIDDLE_SPLIT]]:
150+
; CHECK-NEXT: br i1 [[OR_REDUC]], label %[[FOUND:.*]], label %[[NOTFOUND:.*]]
151+
; CHECK: [[FOUND]]:
152+
; CHECK-NEXT: store i64 56, ptr [[P]], align 8
153+
; CHECK-NEXT: ret i64 1
154+
; CHECK: [[NOTFOUND]]:
155+
; CHECK-NEXT: ret i64 0
156+
;
157+
entry:
158+
%vscale = tail call i64 @llvm.vscale.i64()
159+
%vf = shl nuw nsw i64 %vscale, 1
160+
br label %vector.body
161+
162+
vector.body:
163+
%index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
164+
%arrayidx = getelementptr inbounds ptr, ptr %src, i64 %index
165+
%wide.load = load <vscale x 2 x ptr>, ptr %arrayidx, align 8
166+
%cond = icmp eq <vscale x 2 x ptr> %wide.load, splat(ptr zeroinitializer)
167+
%index.next = add nuw i64 %index, %vf
168+
%or.reduc = tail call i1 @llvm.vector.reduce.or.nxv2i1(<vscale x 2 x i1> %cond)
169+
%iv.cmp = icmp eq i64 %index.next, 4
170+
%exit.cond = or i1 %or.reduc, %iv.cmp
171+
br i1 %exit.cond, label %middle.split, label %vector.body
172+
173+
middle.split:
174+
br i1 %or.reduc, label %found, label %notfound
175+
176+
found:
177+
store i64 56, ptr %p, align 8
178+
ret i64 1
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notfound:
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ret i64 0
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}
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declare i1 @llvm.vector.reduce.or.v2i1(<2 x i1>)
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declare i1 @llvm.vector.reduce.or.nxv2i1(<vscale x 2 x i1>)

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