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[X86] Rename VBROADCASTF128/VBROADCASTI128 to VBROADCASTF128rm/VBROADCASTI128rm (#75040)
Add missing rm postfix to show these are load instructions
1 parent 7b7c85d commit d1deeae

17 files changed

+44
-44
lines changed

‎llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1285,8 +1285,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
12851285
Src2Name = getRegName(MI->getOperand(2).getReg());
12861286
break;
12871287

1288-
case X86::VBROADCASTF128:
1289-
case X86::VBROADCASTI128:
1288+
case X86::VBROADCASTF128rm:
1289+
case X86::VBROADCASTI128rm:
12901290
CASE_AVX512_INS_COMMON(BROADCASTF64X2, Z128, rm)
12911291
CASE_AVX512_INS_COMMON(BROADCASTI64X2, Z128, rm)
12921292
DecodeSubVectorBroadcast(4, 2, ShuffleMask);

‎llvm/lib/Target/X86/X86FixupVectorConstants.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -285,7 +285,7 @@ bool X86FixupVectorConstantsPass::processInstruction(MachineFunction &MF,
285285
case X86::VMOVAPSYrm:
286286
case X86::VMOVUPDYrm:
287287
case X86::VMOVUPSYrm:
288-
return ConvertToBroadcast(0, X86::VBROADCASTF128, X86::VBROADCASTSDYrm,
288+
return ConvertToBroadcast(0, X86::VBROADCASTF128rm, X86::VBROADCASTSDYrm,
289289
X86::VBROADCASTSSYrm, 0, 0, 1);
290290
case X86::VMOVAPDZ128rm:
291291
case X86::VMOVAPSZ128rm:
@@ -318,7 +318,7 @@ bool X86FixupVectorConstantsPass::processInstruction(MachineFunction &MF,
318318
case X86::VMOVDQAYrm:
319319
case X86::VMOVDQUYrm:
320320
return ConvertToBroadcast(
321-
0, HasAVX2 ? X86::VBROADCASTI128 : X86::VBROADCASTF128,
321+
0, HasAVX2 ? X86::VBROADCASTI128rm : X86::VBROADCASTF128rm,
322322
HasAVX2 ? X86::VPBROADCASTQYrm : X86::VBROADCASTSDYrm,
323323
HasAVX2 ? X86::VPBROADCASTDYrm : X86::VBROADCASTSSYrm,
324324
HasAVX2 ? X86::VPBROADCASTWYrm : 0, HasAVX2 ? X86::VPBROADCASTBYrm : 0,

‎llvm/lib/Target/X86/X86InstrSSE.td

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -7093,35 +7093,35 @@ def VBROADCASTSDYrr : avx2_broadcast_rr<0x19, "vbroadcastsd", VR256,
70937093
// halves of a 256-bit vector.
70947094
//
70957095
let mayLoad = 1, hasSideEffects = 0, Predicates = [HasAVX2] in
7096-
def VBROADCASTI128 : AVX8I<0x5A, MRMSrcMem, (outs VR256:$dst),
7097-
(ins i128mem:$src),
7098-
"vbroadcasti128\t{$src, $dst|$dst, $src}", []>,
7099-
Sched<[WriteShuffleLd]>, VEX, VEX_L;
7096+
def VBROADCASTI128rm : AVX8I<0x5A, MRMSrcMem, (outs VR256:$dst),
7097+
(ins i128mem:$src),
7098+
"vbroadcasti128\t{$src, $dst|$dst, $src}", []>,
7099+
Sched<[WriteShuffleLd]>, VEX, VEX_L;
71007100

71017101
let mayLoad = 1, hasSideEffects = 0, Predicates = [HasAVX],
71027102
ExeDomain = SSEPackedSingle in
7103-
def VBROADCASTF128 : AVX8I<0x1A, MRMSrcMem, (outs VR256:$dst),
7104-
(ins f128mem:$src),
7105-
"vbroadcastf128\t{$src, $dst|$dst, $src}", []>,
7106-
Sched<[SchedWriteFShuffle.XMM.Folded]>, VEX, VEX_L;
7103+
def VBROADCASTF128rm : AVX8I<0x1A, MRMSrcMem, (outs VR256:$dst),
7104+
(ins f128mem:$src),
7105+
"vbroadcastf128\t{$src, $dst|$dst, $src}", []>,
7106+
Sched<[SchedWriteFShuffle.XMM.Folded]>, VEX, VEX_L;
71077107

71087108
let Predicates = [HasAVX, NoVLX] in {
71097109
def : Pat<(v4f64 (X86SubVBroadcastld128 addr:$src)),
7110-
(VBROADCASTF128 addr:$src)>;
7110+
(VBROADCASTF128rm addr:$src)>;
71117111
def : Pat<(v8f32 (X86SubVBroadcastld128 addr:$src)),
7112-
(VBROADCASTF128 addr:$src)>;
7112+
(VBROADCASTF128rm addr:$src)>;
71137113
// NOTE: We're using FP instructions here, but execution domain fixing can
71147114
// convert to integer when profitable.
71157115
def : Pat<(v4i64 (X86SubVBroadcastld128 addr:$src)),
7116-
(VBROADCASTF128 addr:$src)>;
7116+
(VBROADCASTF128rm addr:$src)>;
71177117
def : Pat<(v8i32 (X86SubVBroadcastld128 addr:$src)),
7118-
(VBROADCASTF128 addr:$src)>;
7118+
(VBROADCASTF128rm addr:$src)>;
71197119
def : Pat<(v16i16 (X86SubVBroadcastld128 addr:$src)),
7120-
(VBROADCASTF128 addr:$src)>;
7120+
(VBROADCASTF128rm addr:$src)>;
71217121
def : Pat<(v16f16 (X86SubVBroadcastld128 addr:$src)),
7122-
(VBROADCASTF128 addr:$src)>;
7122+
(VBROADCASTF128rm addr:$src)>;
71237123
def : Pat<(v32i8 (X86SubVBroadcastld128 addr:$src)),
7124-
(VBROADCASTF128 addr:$src)>;
7124+
(VBROADCASTF128rm addr:$src)>;
71257125
}
71267126

71277127
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/X86/X86MCInstLower.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1865,8 +1865,8 @@ static void addConstantComments(const MachineInstr *MI,
18651865
// For loads from a constant pool to a vector register, print the constant
18661866
// loaded.
18671867
CASE_ALL_MOV_RM()
1868-
case X86::VBROADCASTF128:
1869-
case X86::VBROADCASTI128:
1868+
case X86::VBROADCASTF128rm:
1869+
case X86::VBROADCASTI128rm:
18701870
case X86::VBROADCASTF32X4Z256rm:
18711871
case X86::VBROADCASTF32X4rm:
18721872
case X86::VBROADCASTF32X8rm:
@@ -1891,8 +1891,8 @@ static void addConstantComments(const MachineInstr *MI,
18911891
CASE_128_MOV_RM() NumLanes = 1; BitWidth = 128; break;
18921892
CASE_256_MOV_RM() NumLanes = 1; BitWidth = 256; break;
18931893
CASE_512_MOV_RM() NumLanes = 1; BitWidth = 512; break;
1894-
case X86::VBROADCASTF128: NumLanes = 2; BitWidth = 128; break;
1895-
case X86::VBROADCASTI128: NumLanes = 2; BitWidth = 128; break;
1894+
case X86::VBROADCASTF128rm: NumLanes = 2; BitWidth = 128; break;
1895+
case X86::VBROADCASTI128rm: NumLanes = 2; BitWidth = 128; break;
18961896
case X86::VBROADCASTF32X4Z256rm: NumLanes = 2; BitWidth = 128; break;
18971897
case X86::VBROADCASTF32X4rm: NumLanes = 4; BitWidth = 128; break;
18981898
case X86::VBROADCASTF32X8rm: NumLanes = 2; BitWidth = 256; break;

‎llvm/lib/Target/X86/X86ReplaceableInstrs.def

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -202,7 +202,7 @@ ENTRY(VBROADCASTSSYrr, VBROADCASTSSYrr, VPBROADCASTDYrr)
202202
ENTRY(VBROADCASTSSYrm, VBROADCASTSSYrm, VPBROADCASTDYrm)
203203
ENTRY(VBROADCASTSDYrr, VBROADCASTSDYrr, VPBROADCASTQYrr)
204204
ENTRY(VBROADCASTSDYrm, VBROADCASTSDYrm, VPBROADCASTQYrm)
205-
ENTRY(VBROADCASTF128, VBROADCASTF128, VBROADCASTI128)
205+
ENTRY(VBROADCASTF128rm, VBROADCASTF128rm, VBROADCASTI128rm)
206206
ENTRY(VBLENDPSYrri, VBLENDPSYrri, VPBLENDDYrri)
207207
ENTRY(VBLENDPSYrmi, VBLENDPSYrmi, VPBLENDDYrmi)
208208
ENTRY(VPERMILPSYmi, VPERMILPSYmi, VPSHUFDYmi)

‎llvm/lib/Target/X86/X86SchedAlderlakeP.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1328,7 +1328,7 @@ def ADLPWriteResGroup117 : SchedWriteRes<[ADLPPort02_03_11]> {
13281328
let Latency = 8;
13291329
}
13301330
def : InstRW<[ADLPWriteResGroup117], (instregex "^MMX_MOV(D|Q)64rm$",
1331-
"^VBROADCAST(F|I)128$",
1331+
"^VBROADCAST(F|I)128rm$",
13321332
"^VBROADCASTS(D|S)Yrm$",
13331333
"^VMOV(D|SH|SL)DUPYrm$",
13341334
"^VPBROADCAST(D|Q)Yrm$")>;

‎llvm/lib/Target/X86/X86SchedBroadwell.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -946,8 +946,8 @@ def BWWriteResGroup58 : SchedWriteRes<[BWPort23]> {
946946
let ReleaseAtCycles = [1];
947947
}
948948
def: InstRW<[BWWriteResGroup58], (instregex "LD_F(32|64|80)m")>;
949-
def: InstRW<[BWWriteResGroup58], (instrs VBROADCASTF128,
950-
VBROADCASTI128,
949+
def: InstRW<[BWWriteResGroup58], (instrs VBROADCASTF128rm,
950+
VBROADCASTI128rm,
951951
VBROADCASTSDYrm,
952952
VBROADCASTSSYrm,
953953
VMOVDDUPYrm,

‎llvm/lib/Target/X86/X86SchedHaswell.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -876,8 +876,8 @@ def HWWriteResGroup0_1 : SchedWriteRes<[HWPort23]> {
876876
let NumMicroOps = 1;
877877
let ReleaseAtCycles = [1];
878878
}
879-
def: InstRW<[HWWriteResGroup0_1], (instrs VBROADCASTF128,
880-
VBROADCASTI128,
879+
def: InstRW<[HWWriteResGroup0_1], (instrs VBROADCASTF128rm,
880+
VBROADCASTI128rm,
881881
VBROADCASTSDYrm,
882882
VBROADCASTSSYrm,
883883
VMOVDDUPYrm,

‎llvm/lib/Target/X86/X86SchedIceLake.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1274,8 +1274,8 @@ def ICXWriteResGroup89 : SchedWriteRes<[ICXPort23]> {
12741274
let ReleaseAtCycles = [1];
12751275
}
12761276
def: InstRW<[ICXWriteResGroup89], (instregex "LD_F(32|64|80)m")>;
1277-
def: InstRW<[ICXWriteResGroup89], (instrs VBROADCASTF128,
1278-
VBROADCASTI128,
1277+
def: InstRW<[ICXWriteResGroup89], (instrs VBROADCASTF128rm,
1278+
VBROADCASTI128rm,
12791279
VBROADCASTSDYrm,
12801280
VBROADCASTSSYrm,
12811281
VMOVDDUPYrm,

‎llvm/lib/Target/X86/X86SchedSapphireRapids.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1599,7 +1599,7 @@ def SPRWriteResGroup126 : SchedWriteRes<[SPRPort02_03_11]> {
15991599
let Latency = 8;
16001600
}
16011601
def : InstRW<[SPRWriteResGroup126], (instregex "^MMX_MOV(D|Q)64rm$",
1602-
"^VBROADCAST(F|I)128$",
1602+
"^VBROADCAST(F|I)128rm$",
16031603
"^VBROADCAST(F|I)32X(2|4)Z256rm$",
16041604
"^VBROADCAST(F|I)32X(8|2Z)rm$",
16051605
"^VBROADCAST(F|I)(32|64)X4rm$",

‎llvm/lib/Target/X86/X86SchedSkylakeClient.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1064,8 +1064,8 @@ def SKLWriteResGroup85 : SchedWriteRes<[SKLPort23]> {
10641064
let ReleaseAtCycles = [1];
10651065
}
10661066
def: InstRW<[SKLWriteResGroup85], (instregex "LD_F(32|64|80)m")>;
1067-
def: InstRW<[SKLWriteResGroup85], (instrs VBROADCASTF128,
1068-
VBROADCASTI128,
1067+
def: InstRW<[SKLWriteResGroup85], (instrs VBROADCASTF128rm,
1068+
VBROADCASTI128rm,
10691069
VBROADCASTSDYrm,
10701070
VBROADCASTSSYrm,
10711071
VMOVDDUPYrm,

‎llvm/lib/Target/X86/X86SchedSkylakeServer.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1254,8 +1254,8 @@ def SKXWriteResGroup89 : SchedWriteRes<[SKXPort23]> {
12541254
let ReleaseAtCycles = [1];
12551255
}
12561256
def: InstRW<[SKXWriteResGroup89], (instregex "LD_F(32|64|80)m")>;
1257-
def: InstRW<[SKXWriteResGroup89], (instrs VBROADCASTF128,
1258-
VBROADCASTI128,
1257+
def: InstRW<[SKXWriteResGroup89], (instrs VBROADCASTF128rm,
1258+
VBROADCASTI128rm,
12591259
VBROADCASTSDYrm,
12601260
VBROADCASTSSYrm,
12611261
VMOVDDUPYrm,

‎llvm/lib/Target/X86/X86ScheduleBdVer2.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -933,7 +933,7 @@ def PdWriteVBROADCASTF128 : SchedWriteRes<[PdFPU01, PdFPFMA]> {
933933
let ReleaseAtCycles = [1, 3];
934934
let NumMicroOps = 2;
935935
}
936-
def : InstRW<[PdWriteVBROADCASTF128], (instrs VBROADCASTF128)>;
936+
def : InstRW<[PdWriteVBROADCASTF128], (instrs VBROADCASTF128rm)>;
937937

938938
defm : PdWriteResXMMPair<WriteFVarShuffle, [PdFPU1, PdFPXBR], 3>;
939939
defm : PdWriteResYMMPair<WriteFVarShuffleY, [PdFPU1, PdFPXBR], 3, [2, 2], 2>;

‎llvm/lib/Target/X86/X86ScheduleBtVer2.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -816,7 +816,7 @@ def JWriteVBROADCASTYLd: SchedWriteRes<[JLAGU, JFPU01, JFPX]> {
816816
}
817817
def : InstRW<[JWriteVBROADCASTYLd], (instrs VBROADCASTSDYrm,
818818
VBROADCASTSSYrm,
819-
VBROADCASTF128)>;
819+
VBROADCASTF128rm)>;
820820

821821
def JWriteJVZEROALL: SchedWriteRes<[]> {
822822
let Latency = 90;

‎llvm/lib/Target/X86/X86ScheduleZnver1.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -996,8 +996,8 @@ def ZnWriteBROADCAST : SchedWriteRes<[ZnAGU, ZnFPU13]> {
996996
let Latency = 8;
997997
}
998998
// VBROADCASTF128 / VBROADCASTI128.
999-
def : InstRW<[ZnWriteBROADCAST], (instrs VBROADCASTF128,
1000-
VBROADCASTI128)>;
999+
def : InstRW<[ZnWriteBROADCAST], (instrs VBROADCASTF128rm,
1000+
VBROADCASTI128rm)>;
10011001

10021002
// EXTRACTPS.
10031003
// r32,x,i.

‎llvm/lib/Target/X86/X86ScheduleZnver2.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1004,8 +1004,8 @@ def Zn2WriteBROADCAST : SchedWriteRes<[Zn2AGU, Zn2FPU13]> {
10041004
let Latency = 8;
10051005
}
10061006
// VBROADCASTF128 / VBROADCASTI128.
1007-
def : InstRW<[Zn2WriteBROADCAST], (instrs VBROADCASTF128,
1008-
VBROADCASTI128)>;
1007+
def : InstRW<[Zn2WriteBROADCAST], (instrs VBROADCASTF128rm,
1008+
VBROADCASTI128rm)>;
10091009

10101010
// EXTRACTPS.
10111011
// r32,x,i.

‎llvm/test/CodeGen/X86/evex-to-vex-compress.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -677,7 +677,7 @@ body: |
677677
$ymm0 = VPMOVZXWQZ256rm $rip, 1, $noreg, 0, $noreg
678678
; CHECK: $ymm0 = VPMOVZXWQYrr $xmm0
679679
$ymm0 = VPMOVZXWQZ256rr $xmm0
680-
; CHECK: $ymm0 = VBROADCASTF128 $rip, 1, $noreg, 0, $noreg
680+
; CHECK: $ymm0 = VBROADCASTF128rm $rip, 1, $noreg, 0, $noreg
681681
$ymm0 = VBROADCASTF32X4Z256rm $rip, 1, $noreg, 0, $noreg
682682
; CHECK: $ymm0 = VBROADCASTSDYrm $rip, 1, $noreg, 0, $noreg
683683
$ymm0 = VBROADCASTF32X2Z256rm $rip, 1, $noreg, 0, $noreg
@@ -703,7 +703,7 @@ body: |
703703
$ymm0 = VPBROADCASTWZ256rm $rip, 1, $noreg, 0, $noreg
704704
; CHECK: $ymm0 = VPBROADCASTWYrr $xmm0
705705
$ymm0 = VPBROADCASTWZ256rr $xmm0
706-
; CHECK: $ymm0 = VBROADCASTI128 $rip, 1, $noreg, 0, $noreg
706+
; CHECK: $ymm0 = VBROADCASTI128rm $rip, 1, $noreg, 0, $noreg
707707
$ymm0 = VBROADCASTI32X4Z256rm $rip, 1, $noreg, 0, $noreg
708708
; CHECK: $ymm0 = VPBROADCASTQYrm $rip, 1, $noreg, 0, $noreg
709709
$ymm0 = VBROADCASTI32X2Z256rm $rip, 1, $noreg, 0, $noreg

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