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[AMDGPU][NFCI] Decouple actual register encodings from HWEncoding values. (#69452)
The HWEncoding values currently form a strange mix of actual register codes for some subtargets and types of operands and informational flags. This patch removes the dependency allowing arbitrary changes in the structure of HWEncoding values without breaking register encodings. Such changes, in turn, would make it possible to speed up and simplify getAVOperandEncoding() testing for AGPRs as well as other functions dealing with register codes downstream. They would also allow to maintain the same format of HWEncoding values across our downstream code bases, thus simplifying merging in mainline changes.
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‎llvm/lib/Target/AMDGPU/FLATInstructions.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1978,7 +1978,7 @@ multiclass FLAT_Real_SADDR_RTN_gfx10<bits<7> op> {
19781978
multiclass FLAT_Real_ST_gfx10<bits<7> op> {
19791979
def _ST_gfx10 :
19801980
FLAT_Real_gfx10<op, !cast<FLAT_Pseudo>(NAME#"_ST")> {
1981-
let Inst{54-48} = !cast<int>(EXEC_HI.HWEncoding);
1981+
let Inst{54-48} = EXEC_HI.Index;
19821982
let OtherPredicates = [HasFlatScratchSTMode];
19831983
}
19841984
}
@@ -2199,13 +2199,13 @@ multiclass FLAT_Aliases_gfx11<string ps, string opName, int renamed> {
21992199
multiclass FLAT_Real_Base_gfx11<bits<7> op, string ps, string opName, int renamed = false> :
22002200
FLAT_Aliases_gfx11<ps, opName, renamed> {
22012201
def _gfx11 : FLAT_Real_gfx11<op, !cast<FLAT_Pseudo>(ps), opName> {
2202-
let Inst{54-48} = !cast<int>(SGPR_NULL_gfx11plus.HWEncoding);
2202+
let Inst{54-48} = SGPR_NULL_gfx11plus.Index;
22032203
}
22042204
}
22052205

22062206
multiclass FLAT_Real_RTN_gfx11<bits<7> op, string ps, string opName> {
22072207
def _RTN_gfx11 : FLAT_Real_gfx11<op, !cast<FLAT_Pseudo>(ps#"_RTN"), opName> {
2208-
let Inst{54-48} = !cast<int>(SGPR_NULL_gfx11plus.HWEncoding);
2208+
let Inst{54-48} = SGPR_NULL_gfx11plus.Index;
22092209
}
22102210
}
22112211

@@ -2219,7 +2219,7 @@ multiclass FLAT_Real_SADDR_RTN_gfx11<bits<7> op, string ps, string opName> {
22192219

22202220
multiclass FLAT_Real_ST_gfx11<bits<7> op, string ps, string opName> {
22212221
def _ST_gfx11 : FLAT_Real_gfx11<op, !cast<FLAT_Pseudo>(ps#"_ST"), opName> {
2222-
let Inst{54-48} = !cast<int>(SGPR_NULL_gfx11plus.HWEncoding);
2222+
let Inst{54-48} = SGPR_NULL_gfx11plus.Index;
22232223
let OtherPredicates = [HasFlatScratchSTMode];
22242224
}
22252225
}

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp

Lines changed: 15 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -353,7 +353,8 @@ void AMDGPUMCCodeEmitter::encodeInstruction(const MCInst &MI,
353353
// However, dst is encoded as EXEC for compatibility with SP3.
354354
if (AMDGPU::isGFX10Plus(STI) && isVCMPX64(Desc)) {
355355
assert((Encoding & 0xFF) == 0);
356-
Encoding |= MRI.getEncodingValue(AMDGPU::EXEC_LO);
356+
Encoding |= MRI.getEncodingValue(AMDGPU::EXEC_LO) &
357+
AMDGPU::HWEncoding::REG_IDX_MASK;
357358
}
358359

359360
for (unsigned i = 0; i < bytes; i++) {
@@ -499,11 +500,14 @@ void AMDGPUMCCodeEmitter::getAVOperandEncoding(
499500
const MCInst &MI, unsigned OpNo, APInt &Op,
500501
SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {
501502
unsigned Reg = MI.getOperand(OpNo).getReg();
502-
uint64_t Enc = MRI.getEncodingValue(Reg);
503+
unsigned Enc = MRI.getEncodingValue(Reg);
504+
unsigned Idx = Enc & AMDGPU::HWEncoding::REG_IDX_MASK;
505+
bool IsVGPROrAGPR = Enc & AMDGPU::HWEncoding::IS_VGPR_OR_AGPR;
503506

504507
// VGPR and AGPR have the same encoding, but SrcA and SrcB operands of mfma
505508
// instructions use acc[0:1] modifier bits to distinguish. These bits are
506509
// encoded as a virtual 9th bit of the register for these operands.
510+
bool IsAGPR = false;
507511
if (MRI.getRegClass(AMDGPU::AGPR_32RegClassID).contains(Reg) ||
508512
MRI.getRegClass(AMDGPU::AReg_64RegClassID).contains(Reg) ||
509513
MRI.getRegClass(AMDGPU::AReg_96RegClassID).contains(Reg) ||
@@ -518,9 +522,9 @@ void AMDGPUMCCodeEmitter::getAVOperandEncoding(
518522
MRI.getRegClass(AMDGPU::AReg_384RegClassID).contains(Reg) ||
519523
MRI.getRegClass(AMDGPU::AReg_512RegClassID).contains(Reg) ||
520524
MRI.getRegClass(AMDGPU::AGPR_LO16RegClassID).contains(Reg))
521-
Enc |= 512;
525+
IsAGPR = true;
522526

523-
Op = Enc;
527+
Op = Idx | (IsVGPROrAGPR << 8) | (IsAGPR << 9);
524528
}
525529

526530
static bool needsPCRel(const MCExpr *Expr) {
@@ -551,7 +555,10 @@ void AMDGPUMCCodeEmitter::getMachineOpValue(const MCInst &MI,
551555
SmallVectorImpl<MCFixup> &Fixups,
552556
const MCSubtargetInfo &STI) const {
553557
if (MO.isReg()){
554-
Op = MRI.getEncodingValue(MO.getReg());
558+
unsigned Enc = MRI.getEncodingValue(MO.getReg());
559+
unsigned Idx = Enc & AMDGPU::HWEncoding::REG_IDX_MASK;
560+
bool IsVGPR = Enc & AMDGPU::HWEncoding::IS_VGPR_OR_AGPR;
561+
Op = Idx | (IsVGPR << 8);
555562
return;
556563
}
557564
unsigned OpNo = &MO - MI.begin();
@@ -570,9 +577,9 @@ void AMDGPUMCCodeEmitter::getMachineOpValueT16Lo128(
570577
const MCOperand &MO = MI.getOperand(OpNo);
571578
if (MO.isReg()) {
572579
uint16_t Encoding = MRI.getEncodingValue(MO.getReg());
573-
unsigned RegIdx = Encoding & AMDGPU::EncValues::REG_IDX_MASK;
574-
bool IsHi = Encoding & AMDGPU::EncValues::IS_HI;
575-
bool IsVGPR = Encoding & AMDGPU::EncValues::IS_VGPR;
580+
unsigned RegIdx = Encoding & AMDGPU::HWEncoding::REG_IDX_MASK;
581+
bool IsHi = Encoding & AMDGPU::HWEncoding::IS_HI;
582+
bool IsVGPR = Encoding & AMDGPU::HWEncoding::IS_VGPR_OR_AGPR;
576583
assert((!IsVGPR || isUInt<7>(RegIdx)) && "VGPR0-VGPR127 expected!");
577584
Op = (IsVGPR ? 0x100 : 0) | (IsHi ? 0x80 : 0) | RegIdx;
578585
return;

‎llvm/lib/Target/AMDGPU/SIDefines.h

Lines changed: 9 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -314,7 +314,6 @@ namespace AMDGPU {
314314
namespace EncValues { // Encoding values of enum9/8/7 operands
315315

316316
enum : unsigned {
317-
REG_IDX_MASK = 255,
318317
SGPR_MIN = 0,
319318
SGPR_MAX_SI = 101,
320319
SGPR_MAX_GFX10 = 105,
@@ -331,13 +330,19 @@ enum : unsigned {
331330
VGPR_MIN = 256,
332331
VGPR_MAX = 511,
333332
IS_VGPR = 256, // Indicates VGPR or AGPR
334-
IS_HI = 512, // High 16-bit register.
335333
};
336334

337335
} // namespace EncValues
338-
} // namespace AMDGPU
339336

340-
namespace AMDGPU {
337+
// Register codes as defined in the TableGen's HWEncoding field.
338+
namespace HWEncoding {
339+
enum : unsigned {
340+
REG_IDX_MASK = 0xff,
341+
IS_VGPR_OR_AGPR = 1 << 8,
342+
IS_HI = 1 << 9, // High 16-bit register.
343+
};
344+
} // namespace HWEncoding
345+
341346
namespace CPol {
342347

343348
enum CPol {

‎llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -506,7 +506,7 @@ RegInterval WaitcntBrackets::getRegInterval(const MachineInstr *MI,
506506
RegInterval Result;
507507

508508
unsigned Reg = TRI->getEncodingValue(AMDGPU::getMCReg(Op.getReg(), *ST)) &
509-
AMDGPU::EncValues::REG_IDX_MASK;
509+
AMDGPU::HWEncoding::REG_IDX_MASK;
510510

511511
if (TRI->isVectorRegister(*MRI, Op.getReg())) {
512512
assert(Reg >= Encoding.VGPR0 && Reg <= Encoding.VGPRL);
@@ -1839,10 +1839,10 @@ bool SIInsertWaitcnts::runOnMachineFunction(MachineFunction &MF) {
18391839

18401840
RegisterEncoding Encoding = {};
18411841
Encoding.VGPR0 =
1842-
TRI->getEncodingValue(AMDGPU::VGPR0) & AMDGPU::EncValues::REG_IDX_MASK;
1842+
TRI->getEncodingValue(AMDGPU::VGPR0) & AMDGPU::HWEncoding::REG_IDX_MASK;
18431843
Encoding.VGPRL = Encoding.VGPR0 + NumVGPRsMax - 1;
18441844
Encoding.SGPR0 =
1845-
TRI->getEncodingValue(AMDGPU::SGPR0) & AMDGPU::EncValues::REG_IDX_MASK;
1845+
TRI->getEncodingValue(AMDGPU::SGPR0) & AMDGPU::HWEncoding::REG_IDX_MASK;
18461846
Encoding.SGPRL = Encoding.SGPR0 + NumSGPRsMax - 1;
18471847

18481848
TrackedWaitcntSet.clear();

‎llvm/lib/Target/AMDGPU/SIRegisterInfo.td

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -125,9 +125,15 @@ class SIRegisterTuples<list<SubRegIndex> Indices, RegisterClass RC,
125125
class SIReg <string n, bits<8> regIdx = 0, bit isAGPROrVGPR = 0,
126126
bit isHi = 0> : Register<n> {
127127
let Namespace = "AMDGPU";
128+
129+
// These are generic helper values we use to form actual register
130+
// codes. They should not be assumed to match any particular register
131+
// encodings on any particular subtargets.
128132
let HWEncoding{7-0} = regIdx;
129133
let HWEncoding{8} = isAGPROrVGPR;
130134
let HWEncoding{9} = isHi;
135+
136+
int Index = !cast<int>(regIdx);
131137
}
132138

133139
// For register classes that use TSFlags.
@@ -164,6 +170,8 @@ multiclass SIRegLoHi16 <string n, bits<8> regIdx, bit ArtificialHigh = 1,
164170
let CoveredBySubRegs = !not(ArtificialHigh);
165171
let HWEncoding{7-0} = regIdx;
166172
let HWEncoding{8} = isAGPROrVGPR;
173+
174+
int Index = !cast<int>(regIdx);
167175
}
168176
}
169177

‎llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2108,7 +2108,7 @@ bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI) {
21082108
}
21092109

21102110
bool isHi(unsigned Reg, const MCRegisterInfo &MRI) {
2111-
return MRI.getEncodingValue(Reg) & AMDGPU::EncValues::IS_HI;
2111+
return MRI.getEncodingValue(Reg) & AMDGPU::HWEncoding::IS_HI;
21122112
}
21132113

21142114
#define MAP_REG2REG \

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