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[AArch64] Additional testing for uqshl and regenerate arm64-vshift.ll. NFC
This tries to fill in some missing testing for neon shift intrinsics, and regenerates the existing tests. See D148309 and D148311.
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‎llvm/test/CodeGen/AArch64/add-extract.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
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define i64 @add_i64_ext_load(<1 x i64> %A, ptr %B) nounwind {
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; CHECK-LABEL: add_i64_ext_load:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: ldr x8, [x0]
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; CHECK-NEXT: fmov x9, d0
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; CHECK-NEXT: add x0, x9, x8
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; CHECK-NEXT: ret
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%a = extractelement <1 x i64> %A, i32 0
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%b = load i64, ptr %B
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%c = add i64 %a, %b
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ret i64 %c
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}
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define i64 @sub_i64_ext_load(<1 x i64> %A, ptr %B) nounwind {
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; CHECK-LABEL: sub_i64_ext_load:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: ldr x8, [x0]
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; CHECK-NEXT: fmov x9, d0
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; CHECK-NEXT: sub x0, x9, x8
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; CHECK-NEXT: ret
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%a = extractelement <1 x i64> %A, i32 0
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%b = load i64, ptr %B
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%c = sub i64 %a, %b
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ret i64 %c
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}
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define void @add_i64_ext_load_store(<1 x i64> %A, ptr %B) nounwind {
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; CHECK-LABEL: add_i64_ext_load_store:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: ldr x8, [x0]
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; CHECK-NEXT: fmov x9, d0
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; CHECK-NEXT: add x8, x9, x8
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; CHECK-NEXT: str x8, [x0]
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; CHECK-NEXT: ret
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%a = extractelement <1 x i64> %A, i32 0
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%b = load i64, ptr %B
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%c = add i64 %a, %b
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store i64 %c, ptr %B
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ret void
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}
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define i64 @add_v2i64_ext_load(<2 x i64> %A, ptr %B) nounwind {
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; CHECK-LABEL: add_v2i64_ext_load:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr x8, [x0]
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; CHECK-NEXT: fmov x9, d0
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; CHECK-NEXT: add x0, x9, x8
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; CHECK-NEXT: ret
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%a = extractelement <2 x i64> %A, i32 0
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%b = load i64, ptr %B
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%c = add i64 %a, %b
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ret i64 %c
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}
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define i64 @add_i64_ext_ext(<1 x i64> %A, <1 x i64> %B) nounwind {
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; CHECK-LABEL: add_i64_ext_ext:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: fmov x8, d0
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; CHECK-NEXT: fmov x9, d1
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; CHECK-NEXT: add x0, x8, x9
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; CHECK-NEXT: ret
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%a = extractelement <1 x i64> %A, i32 0
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%b = extractelement <1 x i64> %B, i32 0
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%c = add i64 %a, %b
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ret i64 %c
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}
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define i32 @add_i32_ext_load(<1 x i32> %A, ptr %B) nounwind {
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; CHECK-LABEL: add_i32_ext_load:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: ldr w8, [x0]
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; CHECK-NEXT: fmov w9, s0
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; CHECK-NEXT: add w0, w9, w8
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; CHECK-NEXT: ret
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%a = extractelement <1 x i32> %A, i32 0
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%b = load i32, ptr %B
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%c = add i32 %a, %b
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ret i32 %c
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}
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define i64 @add_i64_ext_ext_test1(<1 x i64> %A, <2 x i64> %B) nounwind {
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; CHECK-LABEL: add_i64_ext_ext_test1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: mov x8, v1.d[1]
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; CHECK-NEXT: fmov x9, d0
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; CHECK-NEXT: fmov x10, d1
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; CHECK-NEXT: add x9, x9, x10
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; CHECK-NEXT: add x0, x9, x8
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; CHECK-NEXT: ret
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%a = extractelement <1 x i64> %A, i32 0
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%b = extractelement <2 x i64> %B, i32 0
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%c = extractelement <2 x i64> %B, i32 1
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%d = add i64 %a, %b
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%e = add i64 %d, %c
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ret i64 %e
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}
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define i64 @sub_i64_ext_ext_test1(<1 x i64> %A, <2 x i64> %B) nounwind {
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; CHECK-LABEL: sub_i64_ext_ext_test1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: mov x8, v1.d[1]
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; CHECK-NEXT: fmov x9, d0
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; CHECK-NEXT: fmov x10, d1
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; CHECK-NEXT: sub x9, x9, x10
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; CHECK-NEXT: sub x0, x9, x8
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; CHECK-NEXT: ret
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%a = extractelement <1 x i64> %A, i32 0
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%b = extractelement <2 x i64> %B, i32 0
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%c = extractelement <2 x i64> %B, i32 1
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%d = sub i64 %a, %b
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%e = sub i64 %d, %c
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ret i64 %e
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}

‎llvm/test/CodeGen/AArch64/arm64-sqshl-uqshl-i64Contant.ll

Lines changed: 37 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,19 +1,53 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi | FileCheck %s
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; Check if sqshl/uqshl with constant shift amout can be selected.
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; Check if sqshl/uqshl with constant shift amount can be selected.
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define i64 @test_vqshld_s64_i(i64 %a) {
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; CHECK-LABEL: test_vqshld_s64_i:
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; CHECK: sqshl {{d[0-9]+}}, {{d[0-9]+}}, #36
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov d0, x0
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; CHECK-NEXT: sqshl d0, d0, #36
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; CHECK-NEXT: fmov x0, d0
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; CHECK-NEXT: ret
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%1 = tail call i64 @llvm.aarch64.neon.sqshl.i64(i64 %a, i64 36)
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ret i64 %1
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}
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define i64 @test_vqshld_u64_i(i64 %a) {
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; CHECK-LABEL: test_vqshld_u64_i:
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; CHECK: uqshl {{d[0-9]+}}, {{d[0-9]+}}, #36
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov d0, x0
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; CHECK-NEXT: uqshl d0, d0, #36
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; CHECK-NEXT: fmov x0, d0
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; CHECK-NEXT: ret
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%1 = tail call i64 @llvm.aarch64.neon.uqshl.i64(i64 %a, i64 36)
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ret i64 %1
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}
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define i32 @test_vqshld_s32_i(i32 %a) {
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; CHECK-LABEL: test_vqshld_s32_i:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov s0, w0
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; CHECK-NEXT: sqshl s0, s0, #16
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%1 = tail call i32 @llvm.aarch64.neon.sqshl.i32(i32 %a, i32 16)
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ret i32 %1
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}
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define i32 @test_vqshld_u32_i(i32 %a) {
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; CHECK-LABEL: test_vqshld_u32_i:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov s0, w0
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; CHECK-NEXT: uqshl s0, s0, #16
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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%1 = tail call i32 @llvm.aarch64.neon.uqshl.i32(i32 %a, i32 16)
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ret i32 %1
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}
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declare i64 @llvm.aarch64.neon.uqshl.i64(i64, i64)
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declare i64 @llvm.aarch64.neon.sqshl.i64(i64, i64)
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declare i32 @llvm.aarch64.neon.uqshl.i32(i32, i32)
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declare i32 @llvm.aarch64.neon.sqshl.i32(i32, i32)

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