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el-evel-ev
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6 files changed

+165
-197
lines changed

6 files changed

+165
-197
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 19 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -15497,24 +15497,28 @@ static SDValue expandMulToBasicOps(SDNode *N, SelectionDAG &DAG,
1549715497
}
1549815498

1549915499
llvm::SmallVector<std::pair<bool, uint64_t>> Factors; // {is_2^M+1, M}
15500+
15501+
while (E > 1) {
15502+
bool Found = false;
15503+
for (int64_t I = BitWidth - 1; I >= 2; --I) {
15504+
uint64_t Factor = 1ULL << I;
15505+
15506+
if (E % (Factor - 1) == 0) {
15507+
Factors.push_back({false, I});
15508+
E /= Factor - 1;
15509+
Found = true;
15510+
break;
15511+
}
1550015512

15501-
while (true) {
15502-
uint64_t I = 2;
15503-
uint64_t Factor = 1ULL << I;
15504-
for (; I < BitWidth && E >= Factor; I++, Factor = 1ULL << I) {
15505-
if (E % (Factor - 1) == 0) {
15506-
Factors.push_back({false, I});
15507-
E /= (Factor - 1);
15508-
break;
15513+
if (E % (Factor + 1) == 0) {
15514+
Factors.push_back({true, I});
15515+
E /= Factor + 1;
15516+
Found = true;
15517+
break;
15518+
}
1550915519
}
15510-
if (E % (Factor + 1) == 0) {
15511-
Factors.push_back({true, I});
15512-
E /= (Factor + 1);
15520+
if (!Found)
1551315521
break;
15514-
}
15515-
}
15516-
if (I >= BitWidth || E < Factor)
15517-
break;
1551815522
}
1551915523

1552015524
SDValue Result;

‎llvm/test/CodeGen/RISCV/mul-expand.ll

Lines changed: 58 additions & 68 deletions
Original file line numberDiff line numberDiff line change
@@ -7,30 +7,22 @@
77
define i32 @muli32_0x555(i32 %a) nounwind {
88
; RV32I-LABEL: muli32_0x555:
99
; RV32I: # %bb.0:
10-
; RV32I-NEXT: slli a1, a0, 2
11-
; RV32I-NEXT: sub a1, a0, a1
12-
; RV32I-NEXT: slli a0, a0, 4
10+
; RV32I-NEXT: slli a1, a0, 6
1311
; RV32I-NEXT: add a0, a1, a0
14-
; RV32I-NEXT: slli a1, a0, 2
12+
; RV32I-NEXT: slli a1, a0, 3
1513
; RV32I-NEXT: sub a1, a1, a0
1614
; RV32I-NEXT: slli a0, a1, 2
17-
; RV32I-NEXT: add a0, a0, a1
18-
; RV32I-NEXT: slli a1, a0, 3
19-
; RV32I-NEXT: sub a0, a1, a0
15+
; RV32I-NEXT: sub a0, a0, a1
2016
; RV32I-NEXT: ret
2117
;
2218
; RV64I-LABEL: muli32_0x555:
2319
; RV64I: # %bb.0:
24-
; RV64I-NEXT: slli a1, a0, 2
25-
; RV64I-NEXT: sub a1, a0, a1
26-
; RV64I-NEXT: slli a0, a0, 4
20+
; RV64I-NEXT: slli a1, a0, 6
2721
; RV64I-NEXT: add a0, a1, a0
28-
; RV64I-NEXT: slli a1, a0, 2
22+
; RV64I-NEXT: slli a1, a0, 3
2923
; RV64I-NEXT: sub a1, a1, a0
3024
; RV64I-NEXT: slli a0, a1, 2
31-
; RV64I-NEXT: add a0, a0, a1
32-
; RV64I-NEXT: slli a1, a0, 3
33-
; RV64I-NEXT: sub a0, a1, a0
25+
; RV64I-NEXT: sub a0, a0, a1
3426
; RV64I-NEXT: ret
3527
%a1 = mul i32 %a, 1365
3628
ret i32 %a1
@@ -50,16 +42,12 @@ define i64 @muli64_0x555(i64 %a) nounwind {
5042
;
5143
; RV64I-LABEL: muli64_0x555:
5244
; RV64I: # %bb.0:
53-
; RV64I-NEXT: slli a1, a0, 2
54-
; RV64I-NEXT: sub a1, a0, a1
55-
; RV64I-NEXT: slli a0, a0, 4
45+
; RV64I-NEXT: slli a1, a0, 6
5646
; RV64I-NEXT: add a0, a1, a0
57-
; RV64I-NEXT: slli a1, a0, 2
47+
; RV64I-NEXT: slli a1, a0, 3
5848
; RV64I-NEXT: sub a1, a1, a0
5949
; RV64I-NEXT: slli a0, a1, 2
60-
; RV64I-NEXT: add a0, a0, a1
61-
; RV64I-NEXT: slli a1, a0, 3
62-
; RV64I-NEXT: sub a0, a1, a0
50+
; RV64I-NEXT: sub a0, a0, a1
6351
; RV64I-NEXT: ret
6452
%a1 = mul i64 %a, 1365
6553
ret i64 %a1
@@ -68,26 +56,26 @@ define i64 @muli64_0x555(i64 %a) nounwind {
6856
define i32 @muli32_0x33333333(i32 %a) nounwind {
6957
; RV32I-LABEL: muli32_0x33333333:
7058
; RV32I: # %bb.0:
71-
; RV32I-NEXT: slli a1, a0, 2
72-
; RV32I-NEXT: sub a1, a1, a0
73-
; RV32I-NEXT: slli a0, a1, 4
74-
; RV32I-NEXT: add a0, a0, a1
59+
; RV32I-NEXT: slli a1, a0, 16
60+
; RV32I-NEXT: add a0, a1, a0
7561
; RV32I-NEXT: slli a1, a0, 8
7662
; RV32I-NEXT: add a0, a1, a0
77-
; RV32I-NEXT: slli a1, a0, 16
63+
; RV32I-NEXT: slli a1, a0, 4
7864
; RV32I-NEXT: add a0, a1, a0
65+
; RV32I-NEXT: slli a1, a0, 2
66+
; RV32I-NEXT: sub a0, a1, a0
7967
; RV32I-NEXT: ret
8068
;
8169
; RV64I-LABEL: muli32_0x33333333:
8270
; RV64I: # %bb.0:
83-
; RV64I-NEXT: slli a1, a0, 2
84-
; RV64I-NEXT: sub a1, a1, a0
85-
; RV64I-NEXT: slli a0, a1, 4
86-
; RV64I-NEXT: add a0, a0, a1
71+
; RV64I-NEXT: slli a1, a0, 16
72+
; RV64I-NEXT: add a0, a1, a0
8773
; RV64I-NEXT: slli a1, a0, 8
8874
; RV64I-NEXT: add a0, a1, a0
89-
; RV64I-NEXT: slli a1, a0, 16
75+
; RV64I-NEXT: slli a1, a0, 4
9076
; RV64I-NEXT: add a0, a1, a0
77+
; RV64I-NEXT: slli a1, a0, 2
78+
; RV64I-NEXT: sub a0, a1, a0
9179
; RV64I-NEXT: ret
9280
%a1 = mul i32 %a, 858993459
9381
ret i32 %a1
@@ -108,14 +96,14 @@ define i64 @muli64_0x33333333(i64 %a) nounwind {
10896
;
10997
; RV64I-LABEL: muli64_0x33333333:
11098
; RV64I: # %bb.0:
111-
; RV64I-NEXT: slli a1, a0, 2
112-
; RV64I-NEXT: sub a1, a1, a0
113-
; RV64I-NEXT: slli a0, a1, 4
114-
; RV64I-NEXT: add a0, a0, a1
99+
; RV64I-NEXT: slli a1, a0, 16
100+
; RV64I-NEXT: add a0, a1, a0
115101
; RV64I-NEXT: slli a1, a0, 8
116102
; RV64I-NEXT: add a0, a1, a0
117-
; RV64I-NEXT: slli a1, a0, 16
103+
; RV64I-NEXT: slli a1, a0, 4
118104
; RV64I-NEXT: add a0, a1, a0
105+
; RV64I-NEXT: slli a1, a0, 2
106+
; RV64I-NEXT: sub a0, a1, a0
119107
; RV64I-NEXT: ret
120108
%a1 = mul i64 %a, 858993459
121109
ret i64 %a1
@@ -124,13 +112,13 @@ define i64 @muli64_0x33333333(i64 %a) nounwind {
124112
define i32 @muli32_0xaaaaaaaa(i32 %a) nounwind {
125113
; RV32I-LABEL: muli32_0xaaaaaaaa:
126114
; RV32I: # %bb.0:
127-
; RV32I-NEXT: slli a1, a0, 2
128-
; RV32I-NEXT: add a0, a1, a0
129-
; RV32I-NEXT: slli a1, a0, 4
115+
; RV32I-NEXT: slli a1, a0, 16
130116
; RV32I-NEXT: add a0, a1, a0
131117
; RV32I-NEXT: slli a1, a0, 8
132118
; RV32I-NEXT: add a0, a1, a0
133-
; RV32I-NEXT: slli a1, a0, 16
119+
; RV32I-NEXT: slli a1, a0, 4
120+
; RV32I-NEXT: add a0, a1, a0
121+
; RV32I-NEXT: slli a1, a0, 2
134122
; RV32I-NEXT: add a0, a1, a0
135123
; RV32I-NEXT: slli a0, a0, 1
136124
; RV32I-NEXT: ret
@@ -265,32 +253,32 @@ define i64 @muli64_0x0fffffff(i64 %a) nounwind {
265253
define i32 @muli32_0xf0f0f0f0f0(i32 %a) nounwind {
266254
; RV32I-LABEL: muli32_0xf0f0f0f0f0:
267255
; RV32I: # %bb.0:
268-
; RV32I-NEXT: slli a1, a0, 2
269-
; RV32I-NEXT: sub a1, a1, a0
270-
; RV32I-NEXT: slli a0, a1, 2
271-
; RV32I-NEXT: add a0, a0, a1
272-
; RV32I-NEXT: slli a1, a0, 8
273-
; RV32I-NEXT: add a0, a1, a0
274256
; RV32I-NEXT: slli a1, a0, 16
275257
; RV32I-NEXT: add a0, a1, a0
258+
; RV32I-NEXT: slli a1, a0, 8
259+
; RV32I-NEXT: add a0, a1, a0
260+
; RV32I-NEXT: slli a1, a0, 4
261+
; RV32I-NEXT: sub a0, a1, a0
276262
; RV32I-NEXT: slli a0, a0, 4
277263
; RV32I-NEXT: ret
278264
;
279265
; RV64I-LABEL: muli32_0xf0f0f0f0f0:
280266
; RV64I: # %bb.0:
281267
; RV64I-NEXT: slli a1, a0, 4
282-
; RV64I-NEXT: slli a2, a0, 8
283-
; RV64I-NEXT: slli a3, a0, 12
284-
; RV64I-NEXT: slli a4, a0, 16
285-
; RV64I-NEXT: sub a2, a2, a1
286-
; RV64I-NEXT: slli a1, a0, 20
287-
; RV64I-NEXT: sub a3, a3, a4
288-
; RV64I-NEXT: slli a4, a0, 24
289-
; RV64I-NEXT: sub a1, a1, a4
290-
; RV64I-NEXT: slli a0, a0, 28
268+
; RV64I-NEXT: slli a2, a0, 12
269+
; RV64I-NEXT: slli a3, a0, 16
270+
; RV64I-NEXT: sub a1, a0, a1
291271
; RV64I-NEXT: sub a2, a2, a3
272+
; RV64I-NEXT: add a1, a1, a2
273+
; RV64I-NEXT: slli a0, a0, 24
292274
; RV64I-NEXT: add a0, a1, a0
293-
; RV64I-NEXT: sub a0, a2, a0
275+
; RV64I-NEXT: slli a1, a0, 16
276+
; RV64I-NEXT: add a0, a1, a0
277+
; RV64I-NEXT: slli a1, a0, 12
278+
; RV64I-NEXT: sub a1, a1, a0
279+
; RV64I-NEXT: slli a0, a1, 8
280+
; RV64I-NEXT: add a0, a0, a1
281+
; RV64I-NEXT: slli a0, a0, 4
294282
; RV64I-NEXT: ret
295283
%a1 = mul i32 %a, -252645136
296284
ret i32 %a1
@@ -312,18 +300,20 @@ define i64 @muli64_0xf0f0f0f0f0(i64 %a) nounwind {
312300
; RV64I-LABEL: muli64_0xf0f0f0f0f0:
313301
; RV64I: # %bb.0:
314302
; RV64I-NEXT: slli a1, a0, 4
315-
; RV64I-NEXT: slli a2, a0, 8
316-
; RV64I-NEXT: slli a3, a0, 12
317-
; RV64I-NEXT: slli a4, a0, 16
318-
; RV64I-NEXT: sub a2, a2, a1
319-
; RV64I-NEXT: slli a1, a0, 20
320-
; RV64I-NEXT: sub a3, a3, a4
321-
; RV64I-NEXT: slli a4, a0, 24
322-
; RV64I-NEXT: sub a1, a1, a4
323-
; RV64I-NEXT: slli a0, a0, 28
303+
; RV64I-NEXT: slli a2, a0, 12
304+
; RV64I-NEXT: slli a3, a0, 16
305+
; RV64I-NEXT: sub a1, a0, a1
324306
; RV64I-NEXT: sub a2, a2, a3
307+
; RV64I-NEXT: add a1, a1, a2
308+
; RV64I-NEXT: slli a0, a0, 24
309+
; RV64I-NEXT: add a0, a1, a0
310+
; RV64I-NEXT: slli a1, a0, 16
325311
; RV64I-NEXT: add a0, a1, a0
326-
; RV64I-NEXT: sub a0, a2, a0
312+
; RV64I-NEXT: slli a1, a0, 12
313+
; RV64I-NEXT: sub a1, a1, a0
314+
; RV64I-NEXT: slli a0, a1, 8
315+
; RV64I-NEXT: add a0, a0, a1
316+
; RV64I-NEXT: slli a0, a0, 4
327317
; RV64I-NEXT: ret
328318
%a1 = mul i64 %a, -252645136
329319
ret i64 %a1
@@ -336,10 +326,10 @@ define i32 @muli32_0xf7f7f7f7(i32 %a) nounwind {
336326
; RV32I-NEXT: add a1, a0, a1
337327
; RV32I-NEXT: slli a0, a0, 8
338328
; RV32I-NEXT: sub a0, a0, a1
339-
; RV32I-NEXT: slli a1, a0, 8
340-
; RV32I-NEXT: add a0, a1, a0
341329
; RV32I-NEXT: slli a1, a0, 16
342330
; RV32I-NEXT: add a0, a1, a0
331+
; RV32I-NEXT: slli a1, a0, 8
332+
; RV32I-NEXT: add a0, a1, a0
343333
; RV32I-NEXT: ret
344334
;
345335
; RV64I-LABEL: muli32_0xf7f7f7f7:

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