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chuongg3chuongg3
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[AArch64][GlobalISel] Select G_ICMP instruction through TableGen
G_ICMP NE => XOR(G_ICMP EQ, -1) moved to Legalizer to allow for combines if they ever come up in the following passes
1 parent b593c0f commit d23dd09

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2 files changed

+125
-35
lines changed

2 files changed

+125
-35
lines changed

‎llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1486,6 +1486,8 @@ define <8 x i8> @vselect_cmp_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
14861486
; CHECK-GI: // %bb.0:
14871487
; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v1.8b
14881488
; CHECK-GI-NEXT: mvn v0.8b, v0.8b
1489+
; CHECK-GI-NEXT: shl v0.8b, v0.8b, #7
1490+
; CHECK-GI-NEXT: sshr v0.8b, v0.8b, #7
14891491
; CHECK-GI-NEXT: bsl v0.8b, v1.8b, v2.8b
14901492
; CHECK-GI-NEXT: ret
14911493
%cmp = icmp ne <8 x i8> %a, %b
@@ -1516,6 +1518,8 @@ define <8 x i8> @vselect_cmpz_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
15161518
; CHECK-GI-NEXT: movi v3.2d, #0000000000000000
15171519
; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v3.8b
15181520
; CHECK-GI-NEXT: mvn v0.8b, v0.8b
1521+
; CHECK-GI-NEXT: shl v0.8b, v0.8b, #7
1522+
; CHECK-GI-NEXT: sshr v0.8b, v0.8b, #7
15191523
; CHECK-GI-NEXT: bsl v0.8b, v1.8b, v2.8b
15201524
; CHECK-GI-NEXT: ret
15211525
%cmp = icmp ne <8 x i8> %a, zeroinitializer
@@ -1574,6 +1578,8 @@ define <8 x i8> @sext_tst(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
15741578
; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
15751579
; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v2.8b
15761580
; CHECK-GI-NEXT: mvn v0.8b, v0.8b
1581+
; CHECK-GI-NEXT: shl v0.8b, v0.8b, #7
1582+
; CHECK-GI-NEXT: sshr v0.8b, v0.8b, #7
15771583
; CHECK-GI-NEXT: ret
15781584
%tmp3 = and <8 x i8> %a, %b
15791585
%tmp4 = icmp ne <8 x i8> %tmp3, zeroinitializer

‎llvm/test/CodeGen/AArch64/neon-compare-instructions.ll

Lines changed: 119 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -73,77 +73,133 @@ define <2 x i64> @cmeq2xi64(<2 x i64> %A, <2 x i64> %B) {
7373
}
7474

7575
define <8 x i8> @cmne8xi8(<8 x i8> %A, <8 x i8> %B) {
76-
; CHECK-LABEL: cmne8xi8:
77-
; CHECK: // %bb.0:
78-
; CHECK-NEXT: cmeq v0.8b, v0.8b, v1.8b
79-
; CHECK-NEXT: mvn v0.8b, v0.8b
80-
; CHECK-NEXT: ret
76+
; CHECK-SD-LABEL: cmne8xi8:
77+
; CHECK-SD: // %bb.0:
78+
; CHECK-SD-NEXT: cmeq v0.8b, v0.8b, v1.8b
79+
; CHECK-SD-NEXT: mvn v0.8b, v0.8b
80+
; CHECK-SD-NEXT: ret
81+
;
82+
; CHECK-GI-LABEL: cmne8xi8:
83+
; CHECK-GI: // %bb.0:
84+
; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v1.8b
85+
; CHECK-GI-NEXT: mvn v0.8b, v0.8b
86+
; CHECK-GI-NEXT: shl v0.8b, v0.8b, #7
87+
; CHECK-GI-NEXT: sshr v0.8b, v0.8b, #7
88+
; CHECK-GI-NEXT: ret
8189
%tmp3 = icmp ne <8 x i8> %A, %B
8290
%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
8391
ret <8 x i8> %tmp4
8492
}
8593

8694
define <16 x i8> @cmne16xi8(<16 x i8> %A, <16 x i8> %B) {
87-
; CHECK-LABEL: cmne16xi8:
88-
; CHECK: // %bb.0:
89-
; CHECK-NEXT: cmeq v0.16b, v0.16b, v1.16b
90-
; CHECK-NEXT: mvn v0.16b, v0.16b
91-
; CHECK-NEXT: ret
95+
; CHECK-SD-LABEL: cmne16xi8:
96+
; CHECK-SD: // %bb.0:
97+
; CHECK-SD-NEXT: cmeq v0.16b, v0.16b, v1.16b
98+
; CHECK-SD-NEXT: mvn v0.16b, v0.16b
99+
; CHECK-SD-NEXT: ret
100+
;
101+
; CHECK-GI-LABEL: cmne16xi8:
102+
; CHECK-GI: // %bb.0:
103+
; CHECK-GI-NEXT: cmeq v0.16b, v0.16b, v1.16b
104+
; CHECK-GI-NEXT: mvn v0.16b, v0.16b
105+
; CHECK-GI-NEXT: shl v0.16b, v0.16b, #7
106+
; CHECK-GI-NEXT: sshr v0.16b, v0.16b, #7
107+
; CHECK-GI-NEXT: ret
92108
%tmp3 = icmp ne <16 x i8> %A, %B
93109
%tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
94110
ret <16 x i8> %tmp4
95111
}
96112

97113
define <4 x i16> @cmne4xi16(<4 x i16> %A, <4 x i16> %B) {
98-
; CHECK-LABEL: cmne4xi16:
99-
; CHECK: // %bb.0:
100-
; CHECK-NEXT: cmeq v0.4h, v0.4h, v1.4h
101-
; CHECK-NEXT: mvn v0.8b, v0.8b
102-
; CHECK-NEXT: ret
114+
; CHECK-SD-LABEL: cmne4xi16:
115+
; CHECK-SD: // %bb.0:
116+
; CHECK-SD-NEXT: cmeq v0.4h, v0.4h, v1.4h
117+
; CHECK-SD-NEXT: mvn v0.8b, v0.8b
118+
; CHECK-SD-NEXT: ret
119+
;
120+
; CHECK-GI-LABEL: cmne4xi16:
121+
; CHECK-GI: // %bb.0:
122+
; CHECK-GI-NEXT: cmeq v0.4h, v0.4h, v1.4h
123+
; CHECK-GI-NEXT: mvn v0.8b, v0.8b
124+
; CHECK-GI-NEXT: shl v0.4h, v0.4h, #15
125+
; CHECK-GI-NEXT: sshr v0.4h, v0.4h, #15
126+
; CHECK-GI-NEXT: ret
103127
%tmp3 = icmp ne <4 x i16> %A, %B
104128
%tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
105129
ret <4 x i16> %tmp4
106130
}
107131

108132
define <8 x i16> @cmne8xi16(<8 x i16> %A, <8 x i16> %B) {
109-
; CHECK-LABEL: cmne8xi16:
110-
; CHECK: // %bb.0:
111-
; CHECK-NEXT: cmeq v0.8h, v0.8h, v1.8h
112-
; CHECK-NEXT: mvn v0.16b, v0.16b
113-
; CHECK-NEXT: ret
133+
; CHECK-SD-LABEL: cmne8xi16:
134+
; CHECK-SD: // %bb.0:
135+
; CHECK-SD-NEXT: cmeq v0.8h, v0.8h, v1.8h
136+
; CHECK-SD-NEXT: mvn v0.16b, v0.16b
137+
; CHECK-SD-NEXT: ret
138+
;
139+
; CHECK-GI-LABEL: cmne8xi16:
140+
; CHECK-GI: // %bb.0:
141+
; CHECK-GI-NEXT: cmeq v0.8h, v0.8h, v1.8h
142+
; CHECK-GI-NEXT: mvn v0.16b, v0.16b
143+
; CHECK-GI-NEXT: shl v0.8h, v0.8h, #15
144+
; CHECK-GI-NEXT: sshr v0.8h, v0.8h, #15
145+
; CHECK-GI-NEXT: ret
114146
%tmp3 = icmp ne <8 x i16> %A, %B
115147
%tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
116148
ret <8 x i16> %tmp4
117149
}
118150

119151
define <2 x i32> @cmne2xi32(<2 x i32> %A, <2 x i32> %B) {
120-
; CHECK-LABEL: cmne2xi32:
121-
; CHECK: // %bb.0:
122-
; CHECK-NEXT: cmeq v0.2s, v0.2s, v1.2s
123-
; CHECK-NEXT: mvn v0.8b, v0.8b
124-
; CHECK-NEXT: ret
152+
; CHECK-SD-LABEL: cmne2xi32:
153+
; CHECK-SD: // %bb.0:
154+
; CHECK-SD-NEXT: cmeq v0.2s, v0.2s, v1.2s
155+
; CHECK-SD-NEXT: mvn v0.8b, v0.8b
156+
; CHECK-SD-NEXT: ret
157+
;
158+
; CHECK-GI-LABEL: cmne2xi32:
159+
; CHECK-GI: // %bb.0:
160+
; CHECK-GI-NEXT: cmeq v0.2s, v0.2s, v1.2s
161+
; CHECK-GI-NEXT: mvn v0.8b, v0.8b
162+
; CHECK-GI-NEXT: shl v0.2s, v0.2s, #31
163+
; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #31
164+
; CHECK-GI-NEXT: ret
125165
%tmp3 = icmp ne <2 x i32> %A, %B
126166
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
127167
ret <2 x i32> %tmp4
128168
}
129169

130170
define <4 x i32> @cmne4xi32(<4 x i32> %A, <4 x i32> %B) {
131-
; CHECK-LABEL: cmne4xi32:
132-
; CHECK: // %bb.0:
133-
; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s
134-
; CHECK-NEXT: mvn v0.16b, v0.16b
135-
; CHECK-NEXT: ret
171+
; CHECK-SD-LABEL: cmne4xi32:
172+
; CHECK-SD: // %bb.0:
173+
; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, v1.4s
174+
; CHECK-SD-NEXT: mvn v0.16b, v0.16b
175+
; CHECK-SD-NEXT: ret
176+
;
177+
; CHECK-GI-LABEL: cmne4xi32:
178+
; CHECK-GI: // %bb.0:
179+
; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, v1.4s
180+
; CHECK-GI-NEXT: mvn v0.16b, v0.16b
181+
; CHECK-GI-NEXT: shl v0.4s, v0.4s, #31
182+
; CHECK-GI-NEXT: sshr v0.4s, v0.4s, #31
183+
; CHECK-GI-NEXT: ret
136184
%tmp3 = icmp ne <4 x i32> %A, %B
137185
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
138186
ret <4 x i32> %tmp4
139187
}
140188

141189
define <2 x i64> @cmne2xi64(<2 x i64> %A, <2 x i64> %B) {
142-
; CHECK-LABEL: cmne2xi64:
143-
; CHECK: // %bb.0:
144-
; CHECK-NEXT: cmeq v0.2d, v0.2d, v1.2d
145-
; CHECK-NEXT: mvn v0.16b, v0.16b
146-
; CHECK-NEXT: ret
190+
; CHECK-SD-LABEL: cmne2xi64:
191+
; CHECK-SD: // %bb.0:
192+
; CHECK-SD-NEXT: cmeq v0.2d, v0.2d, v1.2d
193+
; CHECK-SD-NEXT: mvn v0.16b, v0.16b
194+
; CHECK-SD-NEXT: ret
195+
;
196+
; CHECK-GI-LABEL: cmne2xi64:
197+
; CHECK-GI: // %bb.0:
198+
; CHECK-GI-NEXT: cmeq v0.2d, v0.2d, v1.2d
199+
; CHECK-GI-NEXT: mvn v0.16b, v0.16b
200+
; CHECK-GI-NEXT: shl v0.2d, v0.2d, #63
201+
; CHECK-GI-NEXT: sshr v0.2d, v0.2d, #63
202+
; CHECK-GI-NEXT: ret
147203
%tmp3 = icmp ne <2 x i64> %A, %B
148204
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64>
149205
ret <2 x i64> %tmp4
@@ -749,6 +805,8 @@ define <8 x i8> @cmtst8xi8(<8 x i8> %A, <8 x i8> %B) {
749805
; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
750806
; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v2.8b
751807
; CHECK-GI-NEXT: mvn v0.8b, v0.8b
808+
; CHECK-GI-NEXT: shl v0.8b, v0.8b, #7
809+
; CHECK-GI-NEXT: sshr v0.8b, v0.8b, #7
752810
; CHECK-GI-NEXT: ret
753811
%tmp3 = and <8 x i8> %A, %B
754812
%tmp4 = icmp ne <8 x i8> %tmp3, zeroinitializer
@@ -768,6 +826,8 @@ define <16 x i8> @cmtst16xi8(<16 x i8> %A, <16 x i8> %B) {
768826
; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
769827
; CHECK-GI-NEXT: cmeq v0.16b, v0.16b, v2.16b
770828
; CHECK-GI-NEXT: mvn v0.16b, v0.16b
829+
; CHECK-GI-NEXT: shl v0.16b, v0.16b, #7
830+
; CHECK-GI-NEXT: sshr v0.16b, v0.16b, #7
771831
; CHECK-GI-NEXT: ret
772832
%tmp3 = and <16 x i8> %A, %B
773833
%tmp4 = icmp ne <16 x i8> %tmp3, zeroinitializer
@@ -787,6 +847,8 @@ define <4 x i16> @cmtst4xi16(<4 x i16> %A, <4 x i16> %B) {
787847
; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
788848
; CHECK-GI-NEXT: cmeq v0.4h, v0.4h, v2.4h
789849
; CHECK-GI-NEXT: mvn v0.8b, v0.8b
850+
; CHECK-GI-NEXT: shl v0.4h, v0.4h, #15
851+
; CHECK-GI-NEXT: sshr v0.4h, v0.4h, #15
790852
; CHECK-GI-NEXT: ret
791853
%tmp3 = and <4 x i16> %A, %B
792854
%tmp4 = icmp ne <4 x i16> %tmp3, zeroinitializer
@@ -806,6 +868,8 @@ define <8 x i16> @cmtst8xi16(<8 x i16> %A, <8 x i16> %B) {
806868
; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
807869
; CHECK-GI-NEXT: cmeq v0.8h, v0.8h, v2.8h
808870
; CHECK-GI-NEXT: mvn v0.16b, v0.16b
871+
; CHECK-GI-NEXT: shl v0.8h, v0.8h, #15
872+
; CHECK-GI-NEXT: sshr v0.8h, v0.8h, #15
809873
; CHECK-GI-NEXT: ret
810874
%tmp3 = and <8 x i16> %A, %B
811875
%tmp4 = icmp ne <8 x i16> %tmp3, zeroinitializer
@@ -825,6 +889,8 @@ define <2 x i32> @cmtst2xi32(<2 x i32> %A, <2 x i32> %B) {
825889
; CHECK-GI-NEXT: and v0.8b, v0.8b, v1.8b
826890
; CHECK-GI-NEXT: cmeq v0.2s, v0.2s, v2.2s
827891
; CHECK-GI-NEXT: mvn v0.8b, v0.8b
892+
; CHECK-GI-NEXT: shl v0.2s, v0.2s, #31
893+
; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #31
828894
; CHECK-GI-NEXT: ret
829895
%tmp3 = and <2 x i32> %A, %B
830896
%tmp4 = icmp ne <2 x i32> %tmp3, zeroinitializer
@@ -844,6 +910,8 @@ define <4 x i32> @cmtst4xi32(<4 x i32> %A, <4 x i32> %B) {
844910
; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
845911
; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, v2.4s
846912
; CHECK-GI-NEXT: mvn v0.16b, v0.16b
913+
; CHECK-GI-NEXT: shl v0.4s, v0.4s, #31
914+
; CHECK-GI-NEXT: sshr v0.4s, v0.4s, #31
847915
; CHECK-GI-NEXT: ret
848916
%tmp3 = and <4 x i32> %A, %B
849917
%tmp4 = icmp ne <4 x i32> %tmp3, zeroinitializer
@@ -863,6 +931,8 @@ define <2 x i64> @cmtst2xi64(<2 x i64> %A, <2 x i64> %B) {
863931
; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
864932
; CHECK-GI-NEXT: cmeq v0.2d, v0.2d, v2.2d
865933
; CHECK-GI-NEXT: mvn v0.16b, v0.16b
934+
; CHECK-GI-NEXT: shl v0.2d, v0.2d, #63
935+
; CHECK-GI-NEXT: sshr v0.2d, v0.2d, #63
866936
; CHECK-GI-NEXT: ret
867937
%tmp3 = and <2 x i64> %A, %B
868938
%tmp4 = icmp ne <2 x i64> %tmp3, zeroinitializer
@@ -1919,6 +1989,8 @@ define <8 x i8> @cmneqz8xi8(<8 x i8> %A) {
19191989
; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
19201990
; CHECK-GI-NEXT: cmeq v0.8b, v0.8b, v1.8b
19211991
; CHECK-GI-NEXT: mvn v0.8b, v0.8b
1992+
; CHECK-GI-NEXT: shl v0.8b, v0.8b, #7
1993+
; CHECK-GI-NEXT: sshr v0.8b, v0.8b, #7
19221994
; CHECK-GI-NEXT: ret
19231995
%tmp3 = icmp ne <8 x i8> %A, zeroinitializer
19241996
%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
@@ -1936,6 +2008,8 @@ define <16 x i8> @cmneqz16xi8(<16 x i8> %A) {
19362008
; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
19372009
; CHECK-GI-NEXT: cmeq v0.16b, v0.16b, v1.16b
19382010
; CHECK-GI-NEXT: mvn v0.16b, v0.16b
2011+
; CHECK-GI-NEXT: shl v0.16b, v0.16b, #7
2012+
; CHECK-GI-NEXT: sshr v0.16b, v0.16b, #7
19392013
; CHECK-GI-NEXT: ret
19402014
%tmp3 = icmp ne <16 x i8> %A, zeroinitializer
19412015
%tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
@@ -1953,6 +2027,8 @@ define <4 x i16> @cmneqz4xi16(<4 x i16> %A) {
19532027
; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
19542028
; CHECK-GI-NEXT: cmeq v0.4h, v0.4h, v1.4h
19552029
; CHECK-GI-NEXT: mvn v0.8b, v0.8b
2030+
; CHECK-GI-NEXT: shl v0.4h, v0.4h, #15
2031+
; CHECK-GI-NEXT: sshr v0.4h, v0.4h, #15
19562032
; CHECK-GI-NEXT: ret
19572033
%tmp3 = icmp ne <4 x i16> %A, zeroinitializer
19582034
%tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
@@ -1970,6 +2046,8 @@ define <8 x i16> @cmneqz8xi16(<8 x i16> %A) {
19702046
; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
19712047
; CHECK-GI-NEXT: cmeq v0.8h, v0.8h, v1.8h
19722048
; CHECK-GI-NEXT: mvn v0.16b, v0.16b
2049+
; CHECK-GI-NEXT: shl v0.8h, v0.8h, #15
2050+
; CHECK-GI-NEXT: sshr v0.8h, v0.8h, #15
19732051
; CHECK-GI-NEXT: ret
19742052
%tmp3 = icmp ne <8 x i16> %A, zeroinitializer
19752053
%tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
@@ -1987,6 +2065,8 @@ define <2 x i32> @cmneqz2xi32(<2 x i32> %A) {
19872065
; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
19882066
; CHECK-GI-NEXT: cmeq v0.2s, v0.2s, v1.2s
19892067
; CHECK-GI-NEXT: mvn v0.8b, v0.8b
2068+
; CHECK-GI-NEXT: shl v0.2s, v0.2s, #31
2069+
; CHECK-GI-NEXT: sshr v0.2s, v0.2s, #31
19902070
; CHECK-GI-NEXT: ret
19912071
%tmp3 = icmp ne <2 x i32> %A, zeroinitializer
19922072
%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
@@ -2004,6 +2084,8 @@ define <4 x i32> @cmneqz4xi32(<4 x i32> %A) {
20042084
; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
20052085
; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, v1.4s
20062086
; CHECK-GI-NEXT: mvn v0.16b, v0.16b
2087+
; CHECK-GI-NEXT: shl v0.4s, v0.4s, #31
2088+
; CHECK-GI-NEXT: sshr v0.4s, v0.4s, #31
20072089
; CHECK-GI-NEXT: ret
20082090
%tmp3 = icmp ne <4 x i32> %A, zeroinitializer
20092091
%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
@@ -2021,6 +2103,8 @@ define <2 x i64> @cmneqz2xi64(<2 x i64> %A) {
20212103
; CHECK-GI-NEXT: movi v1.2d, #0000000000000000
20222104
; CHECK-GI-NEXT: cmeq v0.2d, v0.2d, v1.2d
20232105
; CHECK-GI-NEXT: mvn v0.16b, v0.16b
2106+
; CHECK-GI-NEXT: shl v0.2d, v0.2d, #63
2107+
; CHECK-GI-NEXT: sshr v0.2d, v0.2d, #63
20242108
; CHECK-GI-NEXT: ret
20252109
%tmp3 = icmp ne <2 x i64> %A, zeroinitializer
20262110
%tmp4 = sext <2 x i1> %tmp3 to <2 x i64>

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