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1 parent 01be82c commit d26e672Copy full SHA for d26e672
llvm/test/Transforms/InstCombine/fpextend.ll
@@ -448,3 +448,14 @@ define bfloat @bf16_frem(bfloat %x) {
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%t3 = fptrunc float %t2 to bfloat
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ret bfloat %t3
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}
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+
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+define <4 x float> @v4f32_fadd(<4 x float> %a) {
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+; CHECK-LABEL: @v4f32_fadd(
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+; CHECK-NEXT: [[TMP1:%.*]] = fadd <4 x float> [[A:%.*]], splat (float -1.000000e+00)
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+; CHECK-NEXT: ret <4 x float> [[TMP1]]
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+;
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+ %2 = fpext <4 x float> %a to <4 x double>
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+ %4 = fadd <4 x double> %2, splat (double -1.000000e+00)
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+ %5 = fptrunc <4 x double> %4 to <4 x float>
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+ ret <4 x float> %5
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+}
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