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[AArch64][GlobalISel] Legalize Insert vector element
This attempts to standardize and extend some of the insert vector element lowering. Most notably: - More types are handled by splitting illegal vectors - The index type for G_INSERT_VECTOR_ELT is canonicalized to TLI.getVectorIdxTy(), similar to extact_vector_element. - Some of the existing patterns now have the index type specified to make sure they can apply to GISel too. - The C++ selection code has been removed, relying on tablegen patterns. - G_INSERT_VECTOR_ELT with small GPR input elements are pre-selected to use a i32 type, allowing the existing patterns to apply. - Variable index inserts are lowered in post-legalizer lowering, expanding into a stack store and reload.
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16 files changed

+1109
-771
lines changed

16 files changed

+1109
-771
lines changed

‎llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -141,6 +141,7 @@ def : GINodeEquiv<G_CTLZ_ZERO_UNDEF, ctlz_zero_undef>;
141141
def : GINodeEquiv<G_CTTZ_ZERO_UNDEF, cttz_zero_undef>;
142142
def : GINodeEquiv<G_CTPOP, ctpop>;
143143
def : GINodeEquiv<G_EXTRACT_VECTOR_ELT, extractelt>;
144+
def : GINodeEquiv<G_INSERT_VECTOR_ELT, vector_insert>;
144145
def : GINodeEquiv<G_CONCAT_VECTORS, concat_vectors>;
145146
def : GINodeEquiv<G_BUILD_VECTOR, build_vector>;
146147
def : GINodeEquiv<G_FCEIL, fceil>;

‎llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

Lines changed: 16 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2972,7 +2972,22 @@ bool IRTranslator::translateInsertElement(const User &U,
29722972
Register Res = getOrCreateVReg(U);
29732973
Register Val = getOrCreateVReg(*U.getOperand(0));
29742974
Register Elt = getOrCreateVReg(*U.getOperand(1));
2975-
Register Idx = getOrCreateVReg(*U.getOperand(2));
2975+
const auto &TLI = *MF->getSubtarget().getTargetLowering();
2976+
unsigned PreferredVecIdxWidth = TLI.getVectorIdxTy(*DL).getSizeInBits();
2977+
Register Idx;
2978+
if (auto *CI = dyn_cast<ConstantInt>(U.getOperand(2))) {
2979+
if (CI->getBitWidth() != PreferredVecIdxWidth) {
2980+
APInt NewIdx = CI->getValue().zextOrTrunc(PreferredVecIdxWidth);
2981+
auto *NewIdxCI = ConstantInt::get(CI->getContext(), NewIdx);
2982+
Idx = getOrCreateVReg(*NewIdxCI);
2983+
}
2984+
}
2985+
if (!Idx)
2986+
Idx = getOrCreateVReg(*U.getOperand(2));
2987+
if (MRI->getType(Idx).getSizeInBits() != PreferredVecIdxWidth) {
2988+
const LLT VecIdxTy = LLT::scalar(PreferredVecIdxWidth);
2989+
Idx = MIRBuilder.buildZExtOrTrunc(VecIdxTy, Idx).getReg(0);
2990+
}
29762991
MIRBuilder.buildInsertVectorElement(Res, Val, Elt, Idx);
29772992
return true;
29782993
}

‎llvm/lib/Target/AArch64/AArch64Combine.td

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -114,6 +114,13 @@ def ext: GICombineRule <
114114
(apply [{ applyEXT(*${root}, ${matchinfo}); }])
115115
>;
116116

117+
def insertelt_nonconst: GICombineRule <
118+
(defs root:$root, shuffle_matchdata:$matchinfo),
119+
(match (wip_match_opcode G_INSERT_VECTOR_ELT):$root,
120+
[{ return matchNonConstInsert(*${root}, MRI); }]),
121+
(apply [{ applyNonConstInsert(*${root}, MRI, B); }])
122+
>;
123+
117124
def shuf_to_ins_matchdata : GIDefMatchData<"std::tuple<Register, int, Register, int>">;
118125
def shuf_to_ins: GICombineRule <
119126
(defs root:$root, shuf_to_ins_matchdata:$matchinfo),
@@ -140,8 +147,7 @@ def form_duplane : GICombineRule <
140147
>;
141148

142149
def shuffle_vector_lowering : GICombineGroup<[dup, rev, ext, zip, uzp, trn,
143-
form_duplane,
144-
shuf_to_ins]>;
150+
form_duplane, shuf_to_ins]>;
145151

146152
// Turn G_UNMERGE_VALUES -> G_EXTRACT_VECTOR_ELT's
147153
def vector_unmerge_lowering : GICombineRule <
@@ -269,7 +275,7 @@ def AArch64PostLegalizerLowering
269275
lower_vector_fcmp, form_truncstore,
270276
vector_sext_inreg_to_shift,
271277
unmerge_ext_to_unmerge, lower_mull,
272-
vector_unmerge_lowering]> {
278+
vector_unmerge_lowering, insertelt_nonconst]> {
273279
}
274280

275281
// Post-legalization combines which are primarily optimizations.

‎llvm/lib/Target/AArch64/AArch64InstrAtomics.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -547,10 +547,10 @@ let Predicates = [HasLSE] in {
547547
let Predicates = [HasRCPC3, HasNEON] in {
548548
// LDAP1 loads
549549
def : Pat<(vector_insert (v2i64 VecListOne128:$Rd),
550-
(i64 (acquiring_load<atomic_load_64> GPR64sp:$Rn)), VectorIndexD:$idx),
550+
(i64 (acquiring_load<atomic_load_64> GPR64sp:$Rn)), (i64 VectorIndexD:$idx)),
551551
(LDAP1 VecListOne128:$Rd, VectorIndexD:$idx, GPR64sp:$Rn)>;
552552
def : Pat<(vector_insert (v2f64 VecListOne128:$Rd),
553-
(f64 (bitconvert (i64 (acquiring_load<atomic_load_64> GPR64sp:$Rn)))), VectorIndexD:$idx),
553+
(f64 (bitconvert (i64 (acquiring_load<atomic_load_64> GPR64sp:$Rn)))), (i64 VectorIndexD:$idx)),
554554
(LDAP1 VecListOne128:$Rd, VectorIndexD:$idx, GPR64sp:$Rn)>;
555555
def : Pat<(v1i64 (scalar_to_vector
556556
(i64 (acquiring_load<atomic_load_64> GPR64sp:$Rn)))),

‎llvm/lib/Target/AArch64/AArch64InstrFormats.td

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -7982,7 +7982,7 @@ class SIMDInsFromMain<string size, ValueType vectype,
79827982
"|" # size # "\t$Rd$idx, $Rn}",
79837983
"$Rd = $dst",
79847984
[(set V128:$dst,
7985-
(vector_insert (vectype V128:$Rd), regtype:$Rn, idxtype:$idx))]> {
7985+
(vector_insert (vectype V128:$Rd), regtype:$Rn, (i64 idxtype:$idx)))]> {
79867986
let Inst{14-11} = 0b0011;
79877987
}
79887988

@@ -7996,8 +7996,8 @@ class SIMDInsFromElement<string size, ValueType vectype,
79967996
[(set V128:$dst,
79977997
(vector_insert
79987998
(vectype V128:$Rd),
7999-
(elttype (vector_extract (vectype V128:$Rn), idxtype:$idx2)),
8000-
idxtype:$idx))]>;
7999+
(elttype (vector_extract (vectype V128:$Rn), (i64 idxtype:$idx2))),
8000+
(i64 idxtype:$idx)))]>;
80018001

80028002
class SIMDInsMainMovAlias<string size, Instruction inst,
80038003
RegisterClass regtype, Operand idxtype>

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

Lines changed: 24 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -6551,6 +6551,15 @@ def : Pat<(v8i8 (vector_insert (v8i8 V64:$Rn), (i32 GPR32:$Rm), (i64 VectorIndex
65516551
VectorIndexB:$imm, GPR32:$Rm),
65526552
dsub)>;
65536553

6554+
def : Pat<(v8i8 (vector_insert (v8i8 V64:$Rn), (i8 FPR8:$Rm), (i64 VectorIndexB:$imm))),
6555+
(EXTRACT_SUBREG
6556+
(INSvi8lane (v16i8 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), V64:$Rn, dsub)),
6557+
VectorIndexB:$imm, (v16i8 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR8:$Rm, bsub)), (i64 0)),
6558+
dsub)>;
6559+
def : Pat<(v16i8 (vector_insert (v16i8 V128:$Rn), (i8 FPR8:$Rm), (i64 VectorIndexB:$imm))),
6560+
(INSvi8lane V128:$Rn, VectorIndexB:$imm,
6561+
(v16i8 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR8:$Rm, bsub)), (i64 0))>;
6562+
65546563
// Copy an element at a constant index in one vector into a constant indexed
65556564
// element of another.
65566565
// FIXME refactor to a shared class/dev parameterized on vector type, vector
@@ -6583,26 +6592,26 @@ def : Pat<(v2i64 (int_aarch64_neon_vcopy_lane
65836592
multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64,
65846593
ValueType VTScal, Instruction INS> {
65856594
def : Pat<(VT128 (vector_insert V128:$src,
6586-
(VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
6587-
imm:$Immd)),
6595+
(VTScal (vector_extract (VT128 V128:$Rn), (i64 imm:$Immn))),
6596+
(i64 imm:$Immd))),
65886597
(INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>;
65896598

65906599
def : Pat<(VT128 (vector_insert V128:$src,
6591-
(VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
6592-
imm:$Immd)),
6600+
(VTScal (vector_extract (VT64 V64:$Rn), (i64 imm:$Immn))),
6601+
(i64 imm:$Immd))),
65936602
(INS V128:$src, imm:$Immd,
65946603
(SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>;
65956604

65966605
def : Pat<(VT64 (vector_insert V64:$src,
6597-
(VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
6598-
imm:$Immd)),
6606+
(VTScal (vector_extract (VT128 V128:$Rn), (i64 imm:$Immn))),
6607+
(i64 imm:$Immd))),
65996608
(EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub),
66006609
imm:$Immd, V128:$Rn, imm:$Immn),
66016610
dsub)>;
66026611

66036612
def : Pat<(VT64 (vector_insert V64:$src,
6604-
(VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
6605-
imm:$Immd)),
6613+
(VTScal (vector_extract (VT64 V64:$Rn), (i64 imm:$Immn))),
6614+
(i64 imm:$Immd))),
66066615
(EXTRACT_SUBREG
66076616
(INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd,
66086617
(SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn),
@@ -6621,14 +6630,14 @@ defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, INSvi64lane>;
66216630

66226631
// Insert from bitcast
66236632
// vector_insert(bitcast(f32 src), n, lane) -> INSvi32lane(src, lane, INSERT_SUBREG(-, n), 0)
6624-
def : Pat<(v4i32 (vector_insert v4i32:$src, (i32 (bitconvert (f32 FPR32:$Sn))), imm:$Immd)),
6633+
def : Pat<(v4i32 (vector_insert v4i32:$src, (i32 (bitconvert (f32 FPR32:$Sn))), (i64 imm:$Immd))),
66256634
(INSvi32lane V128:$src, imm:$Immd, (INSERT_SUBREG (IMPLICIT_DEF), FPR32:$Sn, ssub), 0)>;
6626-
def : Pat<(v2i32 (vector_insert v2i32:$src, (i32 (bitconvert (f32 FPR32:$Sn))), imm:$Immd)),
6635+
def : Pat<(v2i32 (vector_insert v2i32:$src, (i32 (bitconvert (f32 FPR32:$Sn))), (i64 imm:$Immd))),
66276636
(EXTRACT_SUBREG
66286637
(INSvi32lane (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), V64:$src, dsub)),
66296638
imm:$Immd, (INSERT_SUBREG (IMPLICIT_DEF), FPR32:$Sn, ssub), 0),
66306639
dsub)>;
6631-
def : Pat<(v2i64 (vector_insert v2i64:$src, (i64 (bitconvert (f64 FPR64:$Sn))), imm:$Immd)),
6640+
def : Pat<(v2i64 (vector_insert v2i64:$src, (i64 (bitconvert (f64 FPR64:$Sn))), (i64 imm:$Immd))),
66326641
(INSvi64lane V128:$src, imm:$Immd, (INSERT_SUBREG (IMPLICIT_DEF), FPR64:$Sn, dsub), 0)>;
66336642

66346643
// bitcast of an extract
@@ -8014,7 +8023,7 @@ def : Pat<(v8bf16 (AArch64dup (bf16 (load GPR64sp:$Rn)))),
80148023
class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex,
80158024
ValueType VTy, ValueType STy, Instruction LD1>
80168025
: Pat<(vector_insert (VTy VecListOne128:$Rd),
8017-
(STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
8026+
(STy (scalar_load GPR64sp:$Rn)), (i64 VecIndex:$idx)),
80188027
(LD1 VecListOne128:$Rd, VecIndex:$idx, GPR64sp:$Rn)>;
80198028

80208029
def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>;
@@ -8037,14 +8046,14 @@ class Ld1Lane128IdxOpPat<SDPatternOperator scalar_load, Operand
80378046
VecIndex, ValueType VTy, ValueType STy,
80388047
Instruction LD1, SDNodeXForm IdxOp>
80398048
: Pat<(vector_insert (VTy VecListOne128:$Rd),
8040-
(STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
8049+
(STy (scalar_load GPR64sp:$Rn)), (i64 VecIndex:$idx)),
80418050
(LD1 VecListOne128:$Rd, (IdxOp VecIndex:$idx), GPR64sp:$Rn)>;
80428051

80438052
class Ld1Lane64IdxOpPat<SDPatternOperator scalar_load, Operand VecIndex,
80448053
ValueType VTy, ValueType STy, Instruction LD1,
80458054
SDNodeXForm IdxOp>
80468055
: Pat<(vector_insert (VTy VecListOne64:$Rd),
8047-
(STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
8056+
(STy (scalar_load GPR64sp:$Rn)), (i64 VecIndex:$idx)),
80488057
(EXTRACT_SUBREG
80498058
(LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),
80508059
(IdxOp VecIndex:$idx), GPR64sp:$Rn),
@@ -8084,7 +8093,7 @@ let Predicates = [IsNeonAvailable] in {
80848093
class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex,
80858094
ValueType VTy, ValueType STy, Instruction LD1>
80868095
: Pat<(vector_insert (VTy VecListOne64:$Rd),
8087-
(STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
8096+
(STy (scalar_load GPR64sp:$Rn)), (i64 VecIndex:$idx)),
80888097
(EXTRACT_SUBREG
80898098
(LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),
80908099
VecIndex:$idx, GPR64sp:$Rn),

‎llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

Lines changed: 30 additions & 62 deletions
Original file line numberDiff line numberDiff line change
@@ -191,7 +191,6 @@ class AArch64InstructionSelector : public InstructionSelector {
191191
MachineInstr *tryAdvSIMDModImmFP(Register Dst, unsigned DstSize, APInt Bits,
192192
MachineIRBuilder &MIRBuilder);
193193

194-
bool selectInsertElt(MachineInstr &I, MachineRegisterInfo &MRI);
195194
bool tryOptConstantBuildVec(MachineInstr &MI, LLT DstTy,
196195
MachineRegisterInfo &MRI);
197196
/// \returns true if a G_BUILD_VECTOR instruction \p MI can be selected as a
@@ -2121,6 +2120,36 @@ bool AArch64InstructionSelector::preISelLower(MachineInstr &I) {
21212120
}
21222121
return false;
21232122
}
2123+
case TargetOpcode::G_INSERT_VECTOR_ELT: {
2124+
// The tablegen patterns for integer insert_vector_elts with small elements
2125+
// will expect the operand to be legalized to a i32 type. This extends the
2126+
// types of i8 and i16 element inserts, so that the existing tablegen
2127+
// patterns can apply.
2128+
Register InsReg = I.getOperand(2).getReg();
2129+
LLT SrcTy = MRI.getType(InsReg);
2130+
if (RBI.getRegBank(InsReg, MRI, TRI)->getID() == AArch64::GPRRegBankID &&
2131+
SrcTy.getSizeInBits() < 32) {
2132+
if (auto *MI = MRI.getVRegDef(InsReg)) {
2133+
if (MI->getOpcode() == TargetOpcode::G_TRUNC &&
2134+
(MRI.getType(MI->getOperand(1).getReg()).getSizeInBits() == 32 ||
2135+
MRI.getType(MI->getOperand(1).getReg()).getSizeInBits() == 64)) {
2136+
I.getOperand(2).setReg(MI->getOperand(1).getReg());
2137+
return true;
2138+
}
2139+
}
2140+
auto Ext = MIB.buildAnyExt(LLT::scalar(32), InsReg);
2141+
Register ExtDst = Ext.getReg(0);
2142+
MRI.setRegBank(ExtDst, RBI.getRegBank(AArch64::GPRRegBankID));
2143+
if (!select(*Ext)) {
2144+
LLVM_DEBUG(
2145+
dbgs() << "Failed to select G_ANYEXT in G_INSERT_VECTOR_ELT");
2146+
return false;
2147+
}
2148+
I.getOperand(2).setReg(ExtDst);
2149+
return true;
2150+
}
2151+
return false;
2152+
}
21242153
default:
21252154
return false;
21262155
}
@@ -3487,8 +3516,6 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
34873516
return selectShuffleVector(I, MRI);
34883517
case TargetOpcode::G_EXTRACT_VECTOR_ELT:
34893518
return selectExtractElt(I, MRI);
3490-
case TargetOpcode::G_INSERT_VECTOR_ELT:
3491-
return selectInsertElt(I, MRI);
34923519
case TargetOpcode::G_CONCAT_VECTORS:
34933520
return selectConcatVectors(I, MRI);
34943521
case TargetOpcode::G_JUMP_TABLE:
@@ -5319,65 +5346,6 @@ bool AArch64InstructionSelector::selectUSMovFromExtend(
53195346
return true;
53205347
}
53215348

5322-
bool AArch64InstructionSelector::selectInsertElt(MachineInstr &I,
5323-
MachineRegisterInfo &MRI) {
5324-
assert(I.getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT);
5325-
5326-
// Get information on the destination.
5327-
Register DstReg = I.getOperand(0).getReg();
5328-
const LLT DstTy = MRI.getType(DstReg);
5329-
unsigned VecSize = DstTy.getSizeInBits();
5330-
5331-
// Get information on the element we want to insert into the destination.
5332-
Register EltReg = I.getOperand(2).getReg();
5333-
const LLT EltTy = MRI.getType(EltReg);
5334-
unsigned EltSize = EltTy.getSizeInBits();
5335-
if (EltSize < 8 || EltSize > 64)
5336-
return false;
5337-
5338-
// Find the definition of the index. Bail out if it's not defined by a
5339-
// G_CONSTANT.
5340-
Register IdxReg = I.getOperand(3).getReg();
5341-
auto VRegAndVal = getIConstantVRegValWithLookThrough(IdxReg, MRI);
5342-
if (!VRegAndVal)
5343-
return false;
5344-
unsigned LaneIdx = VRegAndVal->Value.getSExtValue();
5345-
5346-
// Perform the lane insert.
5347-
Register SrcReg = I.getOperand(1).getReg();
5348-
const RegisterBank &EltRB = *RBI.getRegBank(EltReg, MRI, TRI);
5349-
5350-
if (VecSize < 128) {
5351-
// If the vector we're inserting into is smaller than 128 bits, widen it
5352-
// to 128 to do the insert.
5353-
MachineInstr *ScalarToVec =
5354-
emitScalarToVector(VecSize, &AArch64::FPR128RegClass, SrcReg, MIB);
5355-
if (!ScalarToVec)
5356-
return false;
5357-
SrcReg = ScalarToVec->getOperand(0).getReg();
5358-
}
5359-
5360-
// Create an insert into a new FPR128 register.
5361-
// Note that if our vector is already 128 bits, we end up emitting an extra
5362-
// register.
5363-
MachineInstr *InsMI =
5364-
emitLaneInsert(std::nullopt, SrcReg, EltReg, LaneIdx, EltRB, MIB);
5365-
5366-
if (VecSize < 128) {
5367-
// If we had to widen to perform the insert, then we have to demote back to
5368-
// the original size to get the result we want.
5369-
if (!emitNarrowVector(DstReg, InsMI->getOperand(0).getReg(), MIB, MRI))
5370-
return false;
5371-
} else {
5372-
// No widening needed.
5373-
InsMI->getOperand(0).setReg(DstReg);
5374-
constrainSelectedInstRegOperands(*InsMI, TII, TRI, RBI);
5375-
}
5376-
5377-
I.eraseFromParent();
5378-
return true;
5379-
}
5380-
53815349
MachineInstr *AArch64InstructionSelector::tryAdvSIMDModImm8(
53825350
Register Dst, unsigned DstSize, APInt Bits, MachineIRBuilder &Builder) {
53835351
unsigned int Op;

‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -870,8 +870,15 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
870870
.clampMaxNumElements(1, p0, 2);
871871

872872
getActionDefinitionsBuilder(G_INSERT_VECTOR_ELT)
873-
.legalIf(typeInSet(0, {v16s8, v8s8, v8s16, v4s16, v4s32, v2s32, v2s64}))
874-
.widenVectorEltsToVectorMinSize(0, 64);
873+
.legalIf(
874+
typeInSet(0, {v16s8, v8s8, v8s16, v4s16, v4s32, v2s32, v2s64, v2p0}))
875+
.widenVectorEltsToVectorMinSize(0, 64)
876+
.moreElementsToNextPow2(0)
877+
.clampNumElements(0, v8s8, v16s8)
878+
.clampNumElements(0, v4s16, v8s16)
879+
.clampNumElements(0, v2s32, v4s32)
880+
.clampMaxNumElements(0, s64, 2)
881+
.clampMaxNumElements(0, p0, 2);
875882

876883
getActionDefinitionsBuilder(G_BUILD_VECTOR)
877884
.legalFor({{v8s8, s8},

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