[LSV] Precommit tests

This commit adds tests to introduce bitcasts
for increased vectorization of loads and stores.
NFC.

Author: gandhi56

llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/insert-casts-vectorize.ll

@@ -0,0 +1,89 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=load-store-vectorizer -S -o - < %s | FileCheck %s
+
+define void @merge_i32_2i16_float_4i8(ptr addrspace(1) %ptr) {
+; CHECK-LABEL: define void @merge_i32_2i16_float_4i8(
+; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]]) {
+; CHECK-NEXT:    [[GEP1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[PTR]], i64 0
+; CHECK-NEXT:    [[LOAD1:%.*]] = load i32, ptr addrspace(1) [[GEP1]], align 4
+; CHECK-NEXT:    [[GEP2:%.*]] = getelementptr inbounds <2 x i16>, ptr addrspace(1) [[PTR]], i64 1
+; CHECK-NEXT:    [[LOAD2:%.*]] = load <2 x i16>, ptr addrspace(1) [[GEP2]], align 4
+; CHECK-NEXT:    [[GEP3:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[PTR]], i64 2
+; CHECK-NEXT:    [[LOAD3:%.*]] = load float, ptr addrspace(1) [[GEP3]], align 4
+; CHECK-NEXT:    [[GEP4:%.*]] = getelementptr inbounds <4 x i8>, ptr addrspace(1) [[PTR]], i64 3
+; CHECK-NEXT:    [[LOAD4:%.*]] = load <4 x i8>, ptr addrspace(1) [[GEP4]], align 4
+; CHECK-NEXT:    ret void
+;
+  %gep1 = getelementptr inbounds i32, ptr addrspace(1) %ptr, i64 0
+  %load1 = load i32, ptr addrspace(1) %gep1, align 4
+  %gep2 = getelementptr inbounds <2 x i16>, ptr addrspace(1) %ptr, i64 1
+  %load2 = load <2 x i16>, ptr addrspace(1) %gep2, align 4
+  %gep3 = getelementptr inbounds float, ptr addrspace(1) %ptr, i64 2
+  %load3 = load float, ptr addrspace(1) %gep3, align 4
+  %gep4 = getelementptr inbounds <4 x i8>, ptr addrspace(1) %ptr, i64 3
+  %load4 = load <4 x i8>, ptr addrspace(1) %gep4, align 4
+  ret void
+}
+
+define void @no_merge_i32_i16(ptr addrspace(1) %ptr) {
+; CHECK-LABEL: define void @no_merge_i32_i16(
+; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]]) {
+; CHECK-NEXT:    [[GEP1:%.*]] = getelementptr inbounds ptr, ptr addrspace(1) [[PTR]], i64 0
+; CHECK-NEXT:    [[LOAD1:%.*]] = load i32, ptr addrspace(1) [[GEP1]], align 4
+; CHECK-NEXT:    [[GEP2:%.*]] = getelementptr inbounds ptr, ptr addrspace(1) [[PTR]], i64 1
+; CHECK-NEXT:    [[LOAD2:%.*]] = load i16, ptr addrspace(1) [[GEP2]], align 4
+; CHECK-NEXT:    ret void
+;
+  %gep1 = getelementptr inbounds ptr, ptr addrspace(1) %ptr, i64 0
+  %load1 = load i32, ptr addrspace(1) %gep1, align 4
+  %gep2 = getelementptr inbounds ptr, ptr addrspace(1) %ptr, i64 1
+  %load2 = load i16, ptr addrspace(1) %gep2, align 4
+  ret void
+}
+
+define void @merge_i64_double_ptr(ptr addrspace(1) %ptr, ptr addrspace(2) %ptr2) {
+; CHECK-LABEL: define void @merge_i64_double_ptr(
+; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]], ptr addrspace(2) [[PTR2:%.*]]) {
+; CHECK-NEXT:    [[GEP1:%.*]] = getelementptr inbounds i64, ptr addrspace(1) [[PTR]], i64 0
+; CHECK-NEXT:    [[GEP3:%.*]] = getelementptr inbounds ptr, ptr addrspace(1) [[PTR]], i64 2
+; CHECK-NEXT:    [[TMP1:%.*]] = load <3 x i64>, ptr addrspace(1) [[GEP1]], align 4
+; CHECK-NEXT:    [[LOAD11:%.*]] = extractelement <3 x i64> [[TMP1]], i32 0
+; CHECK-NEXT:    [[LOAD22:%.*]] = extractelement <3 x i64> [[TMP1]], i32 1
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i64 [[LOAD22]] to double
+; CHECK-NEXT:    [[LOAD33:%.*]] = extractelement <3 x i64> [[TMP1]], i32 2
+; CHECK-NEXT:    [[TMP3:%.*]] = inttoptr i64 [[LOAD33]] to ptr
+; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <2 x i64> poison, i64 [[LOAD11]], i32 0
+; CHECK-NEXT:    [[TMP5:%.*]] = bitcast double [[TMP2]] to i64
+; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x i64> [[TMP4]], i64 [[TMP5]], i32 1
+; CHECK-NEXT:    store <2 x i64> [[TMP6]], ptr addrspace(1) [[GEP1]], align 4
+; CHECK-NEXT:    store ptr [[TMP3]], ptr addrspace(1) [[GEP3]], align 4
+; CHECK-NEXT:    ret void
+;
+  %gep1 = getelementptr inbounds i64, ptr addrspace(1) %ptr, i64 0
+  %gep2 = getelementptr inbounds double, ptr addrspace(1) %ptr, i64 1
+  %gep3 = getelementptr inbounds ptr, ptr addrspace(1) %ptr, i64 2
+  %load1 = load i64, ptr addrspace(1) %gep1, align 4
+  %load2 = load double, ptr addrspace(1) %gep2, align 4
+  %load3 = load ptr, ptr addrspace(1) %gep3, align 4
+  store i64 %load1, ptr addrspace(1) %gep1, align 4
+  store double %load2, ptr addrspace(1) %gep2, align 4
+  store ptr %load3, ptr addrspace(1) %gep3, align 4
+  ret void
+}
+
+define void @merge_i16_half(ptr addrspace(1) %ptr) {
+; CHECK-LABEL: define void @merge_i16_half(
+; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]]) {
+; CHECK-NEXT:    [[GEP1:%.*]] = getelementptr inbounds i16, ptr addrspace(1) [[PTR]], i64 0
+; CHECK-NEXT:    [[TMP1:%.*]] = load <2 x i16>, ptr addrspace(1) [[GEP1]], align 4
+; CHECK-NEXT:    [[LOAD11:%.*]] = extractelement <2 x i16> [[TMP1]], i32 0
+; CHECK-NEXT:    [[LOAD22:%.*]] = extractelement <2 x i16> [[TMP1]], i32 1
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i16 [[LOAD22]] to half
+; CHECK-NEXT:    ret void
+;
+  %gep1 = getelementptr inbounds i16, ptr addrspace(1) %ptr, i64 0
+  %load1 = load i16, ptr addrspace(1) %gep1, align 4
+  %gep2 = getelementptr inbounds half, ptr addrspace(1) %ptr, i64 1
+  %load2 = load half, ptr addrspace(1) %gep2, align 4
+  ret void
+}