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[RISCV] Make more vector pseudos commutable
This PR includes: * vadd.vv/vand.vv/vor.vv/vxor.vv * vmseq.vv/vmsne.vv * vmin.vv/vminu.vv/vmax.vv/vmaxu.vv * vmul.vv/vmulh.vv/vmulhu.vv * vwadd.vv/vwaddu.vv * vwmul.vv/vwmulu * vwmacc.vv/vwmaccu.vv * vadc.vvm There is no test change, I may add it later. Fixes part of #64422 Reviewers: michaelmaitland, preames, lukel97, topperc, asb Reviewed By: topperc, lukel97 Pull Request: #88379
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+116
-42
lines changed

2 files changed

+116
-42
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 66 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2718,6 +2718,50 @@ std::string RISCVInstrInfo::createMIROperandComment(
27182718
return Comment;
27192719
}
27202720

2721+
// clang-format off
2722+
#define CASE_RVV_OPCODE_UNMASK_LMUL(OP, LMUL) \
2723+
RISCV::Pseudo##OP##_##LMUL
2724+
2725+
#define CASE_RVV_OPCODE_MASK_LMUL(OP, LMUL) \
2726+
RISCV::Pseudo##OP##_##LMUL##_MASK
2727+
2728+
#define CASE_RVV_OPCODE_LMUL(OP, LMUL) \
2729+
CASE_RVV_OPCODE_UNMASK_LMUL(OP, LMUL): \
2730+
case CASE_RVV_OPCODE_MASK_LMUL(OP, LMUL)
2731+
2732+
#define CASE_RVV_OPCODE_UNMASK_WIDEN(OP) \
2733+
CASE_RVV_OPCODE_UNMASK_LMUL(OP, MF8): \
2734+
case CASE_RVV_OPCODE_UNMASK_LMUL(OP, MF4): \
2735+
case CASE_RVV_OPCODE_UNMASK_LMUL(OP, MF2): \
2736+
case CASE_RVV_OPCODE_UNMASK_LMUL(OP, M1): \
2737+
case CASE_RVV_OPCODE_UNMASK_LMUL(OP, M2): \
2738+
case CASE_RVV_OPCODE_UNMASK_LMUL(OP, M4)
2739+
2740+
#define CASE_RVV_OPCODE_UNMASK(OP) \
2741+
CASE_RVV_OPCODE_UNMASK_WIDEN(OP): \
2742+
case CASE_RVV_OPCODE_UNMASK_LMUL(OP, M8)
2743+
2744+
#define CASE_RVV_OPCODE_MASK_WIDEN(OP) \
2745+
CASE_RVV_OPCODE_MASK_LMUL(OP, MF8): \
2746+
case CASE_RVV_OPCODE_MASK_LMUL(OP, MF4): \
2747+
case CASE_RVV_OPCODE_MASK_LMUL(OP, MF2): \
2748+
case CASE_RVV_OPCODE_MASK_LMUL(OP, M1): \
2749+
case CASE_RVV_OPCODE_MASK_LMUL(OP, M2): \
2750+
case CASE_RVV_OPCODE_MASK_LMUL(OP, M4)
2751+
2752+
#define CASE_RVV_OPCODE_MASK(OP) \
2753+
CASE_RVV_OPCODE_MASK_WIDEN(OP): \
2754+
case CASE_RVV_OPCODE_MASK_LMUL(OP, M8)
2755+
2756+
#define CASE_RVV_OPCODE_WIDEN(OP) \
2757+
CASE_RVV_OPCODE_UNMASK_WIDEN(OP): \
2758+
case CASE_RVV_OPCODE_MASK_WIDEN(OP)
2759+
2760+
#define CASE_RVV_OPCODE(OP) \
2761+
CASE_RVV_OPCODE_UNMASK(OP): \
2762+
case CASE_RVV_OPCODE_MASK(OP)
2763+
// clang-format on
2764+
27212765
// clang-format off
27222766
#define CASE_VMA_OPCODE_COMMON(OP, TYPE, LMUL) \
27232767
RISCV::PseudoV##OP##_##TYPE##_##LMUL
@@ -2798,6 +2842,28 @@ bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
27982842
case RISCV::PseudoCCMOVGPR:
27992843
// Operands 4 and 5 are commutable.
28002844
return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 4, 5);
2845+
case CASE_RVV_OPCODE(VADD_VV):
2846+
case CASE_RVV_OPCODE(VAND_VV):
2847+
case CASE_RVV_OPCODE(VOR_VV):
2848+
case CASE_RVV_OPCODE(VXOR_VV):
2849+
case CASE_RVV_OPCODE_MASK(VMSEQ_VV):
2850+
case CASE_RVV_OPCODE_MASK(VMSNE_VV):
2851+
case CASE_RVV_OPCODE(VMIN_VV):
2852+
case CASE_RVV_OPCODE(VMINU_VV):
2853+
case CASE_RVV_OPCODE(VMAX_VV):
2854+
case CASE_RVV_OPCODE(VMAXU_VV):
2855+
case CASE_RVV_OPCODE(VMUL_VV):
2856+
case CASE_RVV_OPCODE(VMULH_VV):
2857+
case CASE_RVV_OPCODE(VMULHU_VV):
2858+
case CASE_RVV_OPCODE_WIDEN(VWADD_VV):
2859+
case CASE_RVV_OPCODE_WIDEN(VWADDU_VV):
2860+
case CASE_RVV_OPCODE_WIDEN(VWMUL_VV):
2861+
case CASE_RVV_OPCODE_WIDEN(VWMULU_VV):
2862+
case CASE_RVV_OPCODE_WIDEN(VWMACC_VV):
2863+
case CASE_RVV_OPCODE_WIDEN(VWMACCU_VV):
2864+
case CASE_RVV_OPCODE_UNMASK(VADC_VVM):
2865+
// Operands 2 and 3 are commutable.
2866+
return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
28012867
case CASE_VFMA_SPLATS(FMADD):
28022868
case CASE_VFMA_SPLATS(FMSUB):
28032869
case CASE_VFMA_SPLATS(FMACC):

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 50 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -2127,8 +2127,9 @@ multiclass VPseudoBinary<VReg RetClass,
21272127
LMULInfo MInfo,
21282128
string Constraint = "",
21292129
int sew = 0,
2130-
int TargetConstraintType = 1> {
2131-
let VLMul = MInfo.value, SEW=sew in {
2130+
int TargetConstraintType = 1,
2131+
bit Commutable = 0> {
2132+
let VLMul = MInfo.value, SEW=sew, isCommutable = Commutable in {
21322133
defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
21332134
def suffix : VPseudoBinaryNoMaskTU<RetClass, Op1Class, Op2Class,
21342135
Constraint, TargetConstraintType>;
@@ -2167,8 +2168,9 @@ multiclass VPseudoBinaryM<VReg RetClass,
21672168
DAGOperand Op2Class,
21682169
LMULInfo MInfo,
21692170
string Constraint = "",
2170-
int TargetConstraintType = 1> {
2171-
let VLMul = MInfo.value in {
2171+
int TargetConstraintType = 1,
2172+
bit Commutable = 0> {
2173+
let VLMul = MInfo.value, isCommutable = Commutable in {
21722174
def "_" # MInfo.MX : VPseudoBinaryMOutNoMask<RetClass, Op1Class, Op2Class,
21732175
Constraint, TargetConstraintType>;
21742176
let ForceTailAgnostic = true in
@@ -2226,8 +2228,8 @@ multiclass VPseudoTiedBinaryRoundingMode<VReg RetClass,
22262228
}
22272229

22282230

2229-
multiclass VPseudoBinaryV_VV<LMULInfo m, string Constraint = "", int sew = 0> {
2230-
defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m, Constraint, sew>;
2231+
multiclass VPseudoBinaryV_VV<LMULInfo m, string Constraint = "", int sew = 0, bit Commutable = 0> {
2232+
defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m, Constraint, sew, Commutable=Commutable>;
22312233
}
22322234

22332235
multiclass VPseudoBinaryV_VV_RM<LMULInfo m, string Constraint = ""> {
@@ -2331,9 +2333,10 @@ multiclass VPseudoVALU_MM<bit Commutable = 0> {
23312333
// * The destination EEW is greater than the source EEW, the source EMUL is
23322334
// at least 1, and the overlap is in the highest-numbered part of the
23332335
// destination register group is legal. Otherwise, it is illegal.
2334-
multiclass VPseudoBinaryW_VV<LMULInfo m> {
2336+
multiclass VPseudoBinaryW_VV<LMULInfo m, bit Commutable = 0> {
23352337
defm _VV : VPseudoBinary<m.wvrclass, m.vrclass, m.vrclass, m,
2336-
"@earlyclobber $rd", TargetConstraintType=3>;
2338+
"@earlyclobber $rd", TargetConstraintType=3,
2339+
Commutable=Commutable>;
23372340
}
23382341

23392342
multiclass VPseudoBinaryW_VV_RM<LMULInfo m, int sew = 0> {
@@ -2453,7 +2456,9 @@ multiclass VPseudoBinaryV_VM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,
24532456
m.vrclass, m.vrclass, m, CarryIn, Constraint, TargetConstraintType>;
24542457
}
24552458

2456-
multiclass VPseudoTiedBinaryV_VM<LMULInfo m, int TargetConstraintType = 1> {
2459+
multiclass VPseudoTiedBinaryV_VM<LMULInfo m, int TargetConstraintType = 1,
2460+
bit Commutable = 0> {
2461+
let isCommutable = Commutable in
24572462
def "_VVM" # "_" # m.MX:
24582463
VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
24592464
m.vrclass, m.vrclass, m, 1, "",
@@ -2667,9 +2672,11 @@ multiclass PseudoVEXT_VF8 {
26672672
// lowest-numbered part of the source register group".
26682673
// With LMUL<=1 the source and dest occupy a single register so any overlap
26692674
// is in the lowest-numbered part.
2670-
multiclass VPseudoBinaryM_VV<LMULInfo m, int TargetConstraintType = 1> {
2675+
multiclass VPseudoBinaryM_VV<LMULInfo m, int TargetConstraintType = 1,
2676+
bit Commutable = 0> {
26712677
defm _VV : VPseudoBinaryM<VR, m.vrclass, m.vrclass, m,
2672-
!if(!ge(m.octuple, 16), "@earlyclobber $rd", ""), TargetConstraintType>;
2678+
!if(!ge(m.octuple, 16), "@earlyclobber $rd", ""),
2679+
TargetConstraintType, Commutable=Commutable>;
26732680
}
26742681

26752682
multiclass VPseudoBinaryM_VX<LMULInfo m, int TargetConstraintType = 1> {
@@ -2751,10 +2758,11 @@ multiclass VPseudoVSSHT_VV_VX_VI_RM<Operand ImmType = simm5, string Constraint =
27512758
}
27522759
}
27532760

2754-
multiclass VPseudoVALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
2761+
multiclass VPseudoVALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = "",
2762+
bit Commutable = 0> {
27552763
foreach m = MxList in {
27562764
defvar mx = m.MX;
2757-
defm "" : VPseudoBinaryV_VV<m, Constraint>,
2765+
defm "" : VPseudoBinaryV_VV<m, Constraint, Commutable=Commutable>,
27582766
SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", mx,
27592767
forceMergeOpRead=true>;
27602768
defm "" : VPseudoBinaryV_VX<m, Constraint>,
@@ -2804,17 +2812,17 @@ multiclass VPseudoVAALU_VV_VX_RM {
28042812
multiclass VPseudoVMINMAX_VV_VX {
28052813
foreach m = MxList in {
28062814
defvar mx = m.MX;
2807-
defm "" : VPseudoBinaryV_VV<m>,
2815+
defm "" : VPseudoBinaryV_VV<m, Commutable=1>,
28082816
SchedBinary<"WriteVIMinMaxV", "ReadVIMinMaxV", "ReadVIMinMaxV", mx>;
28092817
defm "" : VPseudoBinaryV_VX<m>,
28102818
SchedBinary<"WriteVIMinMaxX", "ReadVIMinMaxV", "ReadVIMinMaxX", mx>;
28112819
}
28122820
}
28132821

2814-
multiclass VPseudoVMUL_VV_VX {
2822+
multiclass VPseudoVMUL_VV_VX<bit Commutable = 0> {
28152823
foreach m = MxList in {
28162824
defvar mx = m.MX;
2817-
defm "" : VPseudoBinaryV_VV<m>,
2825+
defm "" : VPseudoBinaryV_VV<m, Commutable=Commutable>,
28182826
SchedBinary<"WriteVIMulV", "ReadVIMulV", "ReadVIMulV", mx>;
28192827
defm "" : VPseudoBinaryV_VX<m>,
28202828
SchedBinary<"WriteVIMulX", "ReadVIMulV", "ReadVIMulX", mx>;
@@ -2964,10 +2972,10 @@ multiclass VPseudoVALU_VX_VI<Operand ImmType = simm5> {
29642972
}
29652973
}
29662974

2967-
multiclass VPseudoVWALU_VV_VX {
2975+
multiclass VPseudoVWALU_VV_VX<bit Commutable = 0> {
29682976
foreach m = MxListW in {
29692977
defvar mx = m.MX;
2970-
defm "" : VPseudoBinaryW_VV<m>,
2978+
defm "" : VPseudoBinaryW_VV<m, Commutable=Commutable>,
29712979
SchedBinary<"WriteVIWALUV", "ReadVIWALUV", "ReadVIWALUV", mx,
29722980
forceMergeOpRead=true>;
29732981
defm "" : VPseudoBinaryW_VX<m>,
@@ -2976,10 +2984,10 @@ multiclass VPseudoVWALU_VV_VX {
29762984
}
29772985
}
29782986

2979-
multiclass VPseudoVWMUL_VV_VX {
2987+
multiclass VPseudoVWMUL_VV_VX<bit Commutable = 0> {
29802988
foreach m = MxListW in {
29812989
defvar mx = m.MX;
2982-
defm "" : VPseudoBinaryW_VV<m>,
2990+
defm "" : VPseudoBinaryW_VV<m, Commutable=Commutable>,
29832991
SchedBinary<"WriteVIWMulV", "ReadVIWMulV", "ReadVIWMulV", mx,
29842992
forceMergeOpRead=true>;
29852993
defm "" : VPseudoBinaryW_VX<m>,
@@ -3074,7 +3082,7 @@ multiclass VPseudoVMRG_VM_XM_IM {
30743082
multiclass VPseudoVCALU_VM_XM_IM {
30753083
foreach m = MxList in {
30763084
defvar mx = m.MX;
3077-
defm "" : VPseudoTiedBinaryV_VM<m>,
3085+
defm "" : VPseudoTiedBinaryV_VM<m, Commutable=1>,
30783086
SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx,
30793087
forceMergeOpRead=true>;
30803088
defm "" : VPseudoTiedBinaryV_XM<m>,
@@ -3287,10 +3295,10 @@ multiclass VPseudoTernaryV_VF_AAXA_RM<LMULInfo m, FPR_Info f,
32873295
sew, Commutable=1>;
32883296
}
32893297

3290-
multiclass VPseudoTernaryW_VV<LMULInfo m> {
3298+
multiclass VPseudoTernaryW_VV<LMULInfo m, bit Commutable = 0> {
32913299
defvar constraint = "@earlyclobber $rd";
32923300
defm _VV : VPseudoTernaryWithPolicy<m.wvrclass, m.vrclass, m.vrclass, m,
3293-
constraint, /*Commutable*/ 0, TargetConstraintType=3>;
3301+
constraint, Commutable=Commutable, TargetConstraintType=3>;
32943302
}
32953303

32963304
multiclass VPseudoTernaryW_VV_RM<LMULInfo m, int sew = 0> {
@@ -3380,10 +3388,10 @@ multiclass VPseudoVSLD_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
33803388
}
33813389
}
33823390

3383-
multiclass VPseudoVWMAC_VV_VX {
3391+
multiclass VPseudoVWMAC_VV_VX<bit Commutable = 0> {
33843392
foreach m = MxListW in {
33853393
defvar mx = m.MX;
3386-
defm "" : VPseudoTernaryW_VV<m>,
3394+
defm "" : VPseudoTernaryW_VV<m, Commutable=Commutable>,
33873395
SchedTernary<"WriteVIWMulAddV", "ReadVIWMulAddV", "ReadVIWMulAddV",
33883396
"ReadVIWMulAddV", mx>;
33893397
defm "" : VPseudoTernaryW_VX<m>,
@@ -3436,10 +3444,10 @@ multiclass VPseudoVWMAC_VV_VF_BF_RM {
34363444
}
34373445
}
34383446

3439-
multiclass VPseudoVCMPM_VV_VX_VI {
3447+
multiclass VPseudoVCMPM_VV_VX_VI<bit Commutable = 0> {
34403448
foreach m = MxList in {
34413449
defvar mx = m.MX;
3442-
defm "" : VPseudoBinaryM_VV<m, TargetConstraintType=2>,
3450+
defm "" : VPseudoBinaryM_VV<m, TargetConstraintType=2, Commutable=Commutable>,
34433451
SchedBinary<"WriteVICmpV", "ReadVICmpV", "ReadVICmpV", mx>;
34443452
defm "" : VPseudoBinaryM_VX<m, TargetConstraintType=2>,
34453453
SchedBinary<"WriteVICmpX", "ReadVICmpV", "ReadVICmpX", mx>;
@@ -6248,7 +6256,7 @@ defm PseudoVLSEG : VPseudoUSSegLoadFF;
62486256
//===----------------------------------------------------------------------===//
62496257
// 11.1. Vector Single-Width Integer Add and Subtract
62506258
//===----------------------------------------------------------------------===//
6251-
defm PseudoVADD : VPseudoVALU_VV_VX_VI;
6259+
defm PseudoVADD : VPseudoVALU_VV_VX_VI<Commutable=1>;
62526260
defm PseudoVSUB : VPseudoVALU_VV_VX;
62536261
defm PseudoVRSUB : VPseudoVALU_VX_VI;
62546262

@@ -6313,9 +6321,9 @@ foreach vti = AllIntegerVectors in {
63136321
//===----------------------------------------------------------------------===//
63146322
// 11.2. Vector Widening Integer Add/Subtract
63156323
//===----------------------------------------------------------------------===//
6316-
defm PseudoVWADDU : VPseudoVWALU_VV_VX;
6324+
defm PseudoVWADDU : VPseudoVWALU_VV_VX<Commutable=1>;
63176325
defm PseudoVWSUBU : VPseudoVWALU_VV_VX;
6318-
defm PseudoVWADD : VPseudoVWALU_VV_VX;
6326+
defm PseudoVWADD : VPseudoVWALU_VV_VX<Commutable=1>;
63196327
defm PseudoVWSUB : VPseudoVWALU_VV_VX;
63206328
defm PseudoVWADDU : VPseudoVWALU_WV_WX;
63216329
defm PseudoVWSUBU : VPseudoVWALU_WV_WX;
@@ -6346,9 +6354,9 @@ defm PseudoVMSBC : VPseudoVCALUM_V_X<"@earlyclobber $rd">;
63466354
//===----------------------------------------------------------------------===//
63476355
// 11.5. Vector Bitwise Logical Instructions
63486356
//===----------------------------------------------------------------------===//
6349-
defm PseudoVAND : VPseudoVALU_VV_VX_VI;
6350-
defm PseudoVOR : VPseudoVALU_VV_VX_VI;
6351-
defm PseudoVXOR : VPseudoVALU_VV_VX_VI;
6357+
defm PseudoVAND : VPseudoVALU_VV_VX_VI<Commutable=1>;
6358+
defm PseudoVOR : VPseudoVALU_VV_VX_VI<Commutable=1>;
6359+
defm PseudoVXOR : VPseudoVALU_VV_VX_VI<Commutable=1>;
63526360

63536361
//===----------------------------------------------------------------------===//
63546362
// 11.6. Vector Single-Width Bit Shift Instructions
@@ -6366,8 +6374,8 @@ defm PseudoVNSRA : VPseudoVNSHT_WV_WX_WI;
63666374
//===----------------------------------------------------------------------===//
63676375
// 11.8. Vector Integer Comparison Instructions
63686376
//===----------------------------------------------------------------------===//
6369-
defm PseudoVMSEQ : VPseudoVCMPM_VV_VX_VI;
6370-
defm PseudoVMSNE : VPseudoVCMPM_VV_VX_VI;
6377+
defm PseudoVMSEQ : VPseudoVCMPM_VV_VX_VI<Commutable=1>;
6378+
defm PseudoVMSNE : VPseudoVCMPM_VV_VX_VI<Commutable=1>;
63716379
defm PseudoVMSLTU : VPseudoVCMPM_VV_VX;
63726380
defm PseudoVMSLT : VPseudoVCMPM_VV_VX;
63736381
defm PseudoVMSLEU : VPseudoVCMPM_VV_VX_VI;
@@ -6386,9 +6394,9 @@ defm PseudoVMAX : VPseudoVMINMAX_VV_VX;
63866394
//===----------------------------------------------------------------------===//
63876395
// 11.10. Vector Single-Width Integer Multiply Instructions
63886396
//===----------------------------------------------------------------------===//
6389-
defm PseudoVMUL : VPseudoVMUL_VV_VX;
6390-
defm PseudoVMULH : VPseudoVMUL_VV_VX;
6391-
defm PseudoVMULHU : VPseudoVMUL_VV_VX;
6397+
defm PseudoVMUL : VPseudoVMUL_VV_VX<Commutable=1>;
6398+
defm PseudoVMULH : VPseudoVMUL_VV_VX<Commutable=1>;
6399+
defm PseudoVMULHU : VPseudoVMUL_VV_VX<Commutable=1>;
63926400
defm PseudoVMULHSU : VPseudoVMUL_VV_VX;
63936401

63946402
//===----------------------------------------------------------------------===//
@@ -6402,8 +6410,8 @@ defm PseudoVREM : VPseudoVDIV_VV_VX;
64026410
//===----------------------------------------------------------------------===//
64036411
// 11.12. Vector Widening Integer Multiply Instructions
64046412
//===----------------------------------------------------------------------===//
6405-
defm PseudoVWMUL : VPseudoVWMUL_VV_VX;
6406-
defm PseudoVWMULU : VPseudoVWMUL_VV_VX;
6413+
defm PseudoVWMUL : VPseudoVWMUL_VV_VX<Commutable=1>;
6414+
defm PseudoVWMULU : VPseudoVWMUL_VV_VX<Commutable=1>;
64076415
defm PseudoVWMULSU : VPseudoVWMUL_VV_VX;
64086416

64096417
//===----------------------------------------------------------------------===//
@@ -6417,8 +6425,8 @@ defm PseudoVNMSUB : VPseudoVMAC_VV_VX_AAXA;
64176425
//===----------------------------------------------------------------------===//
64186426
// 11.14. Vector Widening Integer Multiply-Add Instructions
64196427
//===----------------------------------------------------------------------===//
6420-
defm PseudoVWMACCU : VPseudoVWMAC_VV_VX;
6421-
defm PseudoVWMACC : VPseudoVWMAC_VV_VX;
6428+
defm PseudoVWMACCU : VPseudoVWMAC_VV_VX<Commutable=1>;
6429+
defm PseudoVWMACC : VPseudoVWMAC_VV_VX<Commutable=1>;
64226430
defm PseudoVWMACCSU : VPseudoVWMAC_VV_VX;
64236431
defm PseudoVWMACCUS : VPseudoVWMAC_VX;
64246432

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