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[RISCV] Rename some Feature* to Tune* (#117966)
These features should be tune features.
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3 files changed

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-14
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‎llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1388,10 +1388,10 @@ def FeatureUnalignedVectorMem
13881388
"true", "Has reasonably performant unaligned vector "
13891389
"loads and stores">;
13901390

1391-
def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
1391+
def TunePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
13921392
"UsePostRAScheduler", "true", "Schedule again after register allocation">;
13931393

1394-
def FeaturePredictableSelectIsExpensive
1394+
def TunePredictableSelectIsExpensive
13951395
: SubtargetFeature<"predictable-select-expensive", "PredictableSelectIsExpensive", "true",
13961396
"Prefer likely predicted branches over selects">;
13971397

‎llvm/lib/Target/RISCV/RISCVProcessors.td

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -95,7 +95,7 @@ def ROCKET : RISCVTuneProcessorModel<"rocket",
9595

9696
defvar SiFive7TuneFeatures = [TuneSiFive7, TuneNoDefaultUnroll,
9797
TuneShortForwardBranchOpt,
98-
FeaturePostRAScheduler];
98+
TunePostRAScheduler];
9999
def SIFIVE_7 : RISCVTuneProcessorModel<"sifive-7-series",
100100
SiFive7Model, SiFive7TuneFeatures>;
101101

@@ -251,7 +251,7 @@ defvar SiFiveP400TuneFeatures = [TuneNoDefaultUnroll,
251251
TuneConditionalCompressedMoveFusion,
252252
TuneLUIADDIFusion,
253253
TuneAUIPCADDIFusion,
254-
FeaturePostRAScheduler];
254+
TunePostRAScheduler];
255255

256256
def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model,
257257
!listconcat(RVA22U64Features,
@@ -300,7 +300,7 @@ def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model,
300300
TuneAUIPCADDIFusion,
301301
TuneNoSinkSplatOperands,
302302
TuneVXRMPipelineFlush,
303-
FeaturePostRAScheduler]>;
303+
TunePostRAScheduler]>;
304304

305305
def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
306306
SyntacoreSCR1Model,
@@ -329,7 +329,7 @@ def SYNTACORE_SCR3_RV32 : RISCVProcessorModel<"syntacore-scr3-rv32",
329329
FeatureStdExtZifencei,
330330
FeatureStdExtM,
331331
FeatureStdExtC],
332-
[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
332+
[TuneNoDefaultUnroll, TunePostRAScheduler]>;
333333

334334
def SYNTACORE_SCR3_RV64 : RISCVProcessorModel<"syntacore-scr3-rv64",
335335
SyntacoreSCR3RV64Model,
@@ -340,7 +340,7 @@ def SYNTACORE_SCR3_RV64 : RISCVProcessorModel<"syntacore-scr3-rv64",
340340
FeatureStdExtM,
341341
FeatureStdExtA,
342342
FeatureStdExtC],
343-
[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
343+
[TuneNoDefaultUnroll, TunePostRAScheduler]>;
344344

345345
def SYNTACORE_SCR4_RV32 : RISCVProcessorModel<"syntacore-scr4-rv32",
346346
SyntacoreSCR4RV32Model,
@@ -352,7 +352,7 @@ def SYNTACORE_SCR4_RV32 : RISCVProcessorModel<"syntacore-scr4-rv32",
352352
FeatureStdExtF,
353353
FeatureStdExtD,
354354
FeatureStdExtC],
355-
[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
355+
[TuneNoDefaultUnroll, TunePostRAScheduler]>;
356356

357357
def SYNTACORE_SCR4_RV64 : RISCVProcessorModel<"syntacore-scr4-rv64",
358358
SyntacoreSCR4RV64Model,
@@ -365,7 +365,7 @@ def SYNTACORE_SCR4_RV64 : RISCVProcessorModel<"syntacore-scr4-rv64",
365365
FeatureStdExtF,
366366
FeatureStdExtD,
367367
FeatureStdExtC],
368-
[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
368+
[TuneNoDefaultUnroll, TunePostRAScheduler]>;
369369

370370
def SYNTACORE_SCR5_RV32 : RISCVProcessorModel<"syntacore-scr5-rv32",
371371
SyntacoreSCR5RV32Model,
@@ -378,7 +378,7 @@ def SYNTACORE_SCR5_RV32 : RISCVProcessorModel<"syntacore-scr5-rv32",
378378
FeatureStdExtF,
379379
FeatureStdExtD,
380380
FeatureStdExtC],
381-
[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
381+
[TuneNoDefaultUnroll, TunePostRAScheduler]>;
382382

383383
def SYNTACORE_SCR5_RV64 : RISCVProcessorModel<"syntacore-scr5-rv64",
384384
SyntacoreSCR5RV64Model,
@@ -391,7 +391,7 @@ def SYNTACORE_SCR5_RV64 : RISCVProcessorModel<"syntacore-scr5-rv64",
391391
FeatureStdExtF,
392392
FeatureStdExtD,
393393
FeatureStdExtC],
394-
[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
394+
[TuneNoDefaultUnroll, TunePostRAScheduler]>;
395395

396396
def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
397397
SyntacoreSCR7Model,
@@ -410,7 +410,7 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
410410
FeatureStdExtZbc,
411411
FeatureStdExtZbs,
412412
FeatureStdExtZkn],
413-
[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
413+
[TuneNoDefaultUnroll, TunePostRAScheduler]>;
414414

415415
def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8",
416416
NoSchedModel,
@@ -432,7 +432,7 @@ def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8",
432432
FeatureUnalignedVectorMem]),
433433
[TuneNoDefaultUnroll,
434434
TuneOptimizedZeroStrideLoad,
435-
FeaturePostRAScheduler]>;
435+
TunePostRAScheduler]>;
436436

437437
def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
438438
NoSchedModel,

‎llvm/test/CodeGen/RISCV/convert-highly-predictable-select-to-branch.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ entry:
1919
}
2020

2121
; Test has highly predictable select according to profile data,
22-
; which should be transformed to a branch on cores with enabled FeaturePredictableSelectIsExpensive
22+
; which should be transformed to a branch on cores with enabled TunePredictableSelectIsExpensive
2323
define i32 @test2(i32 %a) {
2424
; CHEAP-LABEL: test2:
2525
; CHEAP: # %bb.0: # %entry

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