Skip to content

Commit d3a4c18

Browse files
Fix support for strict version of fp to (u)int and (u)int to fp
1 parent 5c3a0fa commit d3a4c18

File tree

1 file changed

+16
-5
lines changed

1 file changed

+16
-5
lines changed

llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

Lines changed: 16 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -3090,6 +3090,8 @@ void DAGTypeLegalizer::SoftPromoteHalfResult(SDNode *N, unsigned ResNo) {
30903090
break;
30913091
case ISD::SELECT: R = SoftPromoteHalfRes_SELECT(N); break;
30923092
case ISD::SELECT_CC: R = SoftPromoteHalfRes_SELECT_CC(N); break;
3093+
case ISD::STRICT_SINT_TO_FP:
3094+
case ISD::STRICT_UINT_TO_FP:
30933095
case ISD::SINT_TO_FP:
30943096
case ISD::UINT_TO_FP: R = SoftPromoteHalfRes_XINT_TO_FP(N); break;
30953097
case ISD::UNDEF: R = SoftPromoteHalfRes_UNDEF(N); break;
@@ -3311,7 +3313,12 @@ SDValue DAGTypeLegalizer::SoftPromoteHalfRes_XINT_TO_FP(SDNode *N) {
33113313
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), OVT);
33123314
SDLoc dl(N);
33133315

3314-
SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
3316+
SDValue Op = N->getOperand(N->isStrictFPOpcode() ? 1 : 0);
3317+
3318+
bool Signed = N->getOpcode() == ISD::SINT_TO_FP ||
3319+
N->getOpcode() == ISD::STRICT_SINT_TO_FP;
3320+
SDValue Res =
3321+
DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, dl, NVT, Op);
33153322

33163323
// Round the value to the softened type.
33173324
return DAG.getNode(GetPromotionOpcode(NVT, OVT), dl, MVT::i16, Res);
@@ -3396,6 +3403,8 @@ bool DAGTypeLegalizer::SoftPromoteHalfOperand(SDNode *N, unsigned OpNo) {
33963403

33973404
case ISD::BITCAST: Res = SoftPromoteHalfOp_BITCAST(N); break;
33983405
case ISD::FCOPYSIGN: Res = SoftPromoteHalfOp_FCOPYSIGN(N, OpNo); break;
3406+
case ISD::STRICT_FP_TO_SINT:
3407+
case ISD::STRICT_FP_TO_UINT:
33993408
case ISD::FP_TO_SINT:
34003409
case ISD::FP_TO_UINT: Res = SoftPromoteHalfOp_FP_TO_XINT(N); break;
34013410
case ISD::FP_TO_SINT_SAT:
@@ -3422,8 +3431,7 @@ bool DAGTypeLegalizer::SoftPromoteHalfOperand(SDNode *N, unsigned OpNo) {
34223431

34233432
assert(Res.getNode() != N && "Expected a new node!");
34243433

3425-
assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
3426-
"Invalid operand expansion");
3434+
assert(Res.getValueType() == N->getValueType(0) && "Invalid operand expansion");
34273435

34283436
ReplaceValueWith(SDValue(N, 0), Res);
34293437
return false;
@@ -3479,7 +3487,7 @@ SDValue DAGTypeLegalizer::SoftPromoteHalfOp_FP_EXTEND(SDNode *N) {
34793487

34803488
SDValue DAGTypeLegalizer::SoftPromoteHalfOp_FP_TO_XINT(SDNode *N) {
34813489
EVT RVT = N->getValueType(0);
3482-
SDValue Op = N->getOperand(0);
3490+
SDValue Op = N->getOperand(N->isStrictFPOpcode() ? 1 : 0);
34833491
EVT SVT = Op.getValueType();
34843492
SDLoc dl(N);
34853493

@@ -3489,7 +3497,10 @@ SDValue DAGTypeLegalizer::SoftPromoteHalfOp_FP_TO_XINT(SDNode *N) {
34893497

34903498
SDValue Res = DAG.getNode(GetPromotionOpcode(SVT, RVT), dl, NVT, Op);
34913499

3492-
return DAG.getNode(N->getOpcode(), dl, N->getValueType(0), Res);
3500+
bool Signed = N->getOpcode() == ISD::FP_TO_SINT ||
3501+
N->getOpcode() == ISD::STRICT_FP_TO_SINT;
3502+
return DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, dl,
3503+
N->getValueType(0), Res);
34933504
}
34943505

34953506
SDValue DAGTypeLegalizer::SoftPromoteHalfOp_FP_TO_XINT_SAT(SDNode *N) {

0 commit comments

Comments
 (0)