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[RISCV] Add coverage for vsetvli insertion at O0 [nfc]
In review around #94686, we had a discussion about a possible O0 specific miscompile case without test coverage. The particular case turned out not be possible to exercise in practice, but improving our test coverage remains a good idea if we're going to have differences in the dataflow with and without live intervals.
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‎llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-O0.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+m,+f,+d,+a,+c,+v \
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; RUN: -target-abi=lp64d -verify-machineinstrs -O0 < %s | FileCheck %s
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declare i64 @llvm.riscv.vsetvli(i64, i64, i64)
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declare i64 @llvm.riscv.vsetvlimax(i64, i64)
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declare <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(
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<vscale x 1 x double>,
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<vscale x 1 x double>,
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<vscale x 1 x double>,
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i64, i64)
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declare <vscale x 1 x i64> @llvm.riscv.vle.mask.nxv1i64(
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<vscale x 1 x i64>,
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ptr,
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<vscale x 1 x i1>,
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i64, i64)
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define <2 x double> @fixed_length(<2 x double> %a, <2 x double> %b) nounwind {
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; CHECK-LABEL: fixed_length:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmv1r.v v10, v9
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; CHECK-NEXT: # kill: def $v11 killed $v10
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; CHECK-NEXT: # kill: def $v9 killed $v8
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; CHECK-NEXT: # implicit-def: $v9
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; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
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; CHECK-NEXT: vfadd.vv v9, v8, v10
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; CHECK-NEXT: # implicit-def: $v8
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; CHECK-NEXT: vfadd.vv v8, v9, v10
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; CHECK-NEXT: ret
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entry:
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%1 = fadd <2 x double> %a, %b
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%2 = fadd <2 x double> %1, %b
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ret <2 x double> %2
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}
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define <vscale x 1 x double> @scalable(<vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
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; CHECK-LABEL: scalable:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmv1r.v v10, v9
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; CHECK-NEXT: # implicit-def: $v9
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; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
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; CHECK-NEXT: vfadd.vv v9, v8, v10
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; CHECK-NEXT: # implicit-def: $v8
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; CHECK-NEXT: vfadd.vv v8, v9, v10
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; CHECK-NEXT: ret
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entry:
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%1 = fadd <vscale x 1 x double> %a, %b
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%2 = fadd <vscale x 1 x double> %1, %b
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ret <vscale x 1 x double> %2
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}
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define <vscale x 1 x double> @intrinsic_same_vlmax(<vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
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; CHECK-LABEL: intrinsic_same_vlmax:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmv1r.v v10, v9
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; CHECK-NEXT: vsetvli a0, zero, e64, m1, tu, ma
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; CHECK-NEXT: # implicit-def: $v9
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; CHECK-NEXT: vfadd.vv v9, v8, v10
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; CHECK-NEXT: # implicit-def: $v8
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; CHECK-NEXT: vfadd.vv v8, v9, v10
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i64 @llvm.riscv.vsetvlimax(i64 2, i64 7)
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%1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(
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<vscale x 1 x double> undef,
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<vscale x 1 x double> %a,
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<vscale x 1 x double> %b,
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i64 7, i64 %0)
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%2 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(
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<vscale x 1 x double> undef,
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<vscale x 1 x double> %1,
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<vscale x 1 x double> %b,
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i64 7, i64 %0)
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ret <vscale x 1 x double> %2
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}
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define <vscale x 1 x double> @intrinsic_same_avl_imm(<vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
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; CHECK-LABEL: intrinsic_same_avl_imm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmv1r.v v10, v9
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; CHECK-NEXT: vsetivli a0, 2, e64, m1, tu, ma
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; CHECK-NEXT: # implicit-def: $v9
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; CHECK-NEXT: vfadd.vv v9, v8, v10
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; CHECK-NEXT: # implicit-def: $v8
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; CHECK-NEXT: vfadd.vv v8, v9, v10
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i64 @llvm.riscv.vsetvli(i64 2, i64 2, i64 7)
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%1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(
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<vscale x 1 x double> undef,
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<vscale x 1 x double> %a,
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<vscale x 1 x double> %b,
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i64 7, i64 %0)
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%2 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(
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<vscale x 1 x double> undef,
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<vscale x 1 x double> %1,
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<vscale x 1 x double> %b,
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i64 7, i64 %0)
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ret <vscale x 1 x double> %2
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}
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define <vscale x 1 x double> @intrinsic_same_avl_reg(i64 %avl, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
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; CHECK-LABEL: intrinsic_same_avl_reg:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmv1r.v v10, v9
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; CHECK-NEXT: vsetvli a0, a0, e64, m1, tu, ma
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; CHECK-NEXT: # implicit-def: $v9
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; CHECK-NEXT: vfadd.vv v9, v8, v10
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; CHECK-NEXT: # implicit-def: $v8
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; CHECK-NEXT: vfadd.vv v8, v9, v10
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 7)
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%1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(
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<vscale x 1 x double> undef,
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<vscale x 1 x double> %a,
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<vscale x 1 x double> %b,
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i64 7, i64 %0)
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%2 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(
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<vscale x 1 x double> undef,
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<vscale x 1 x double> %1,
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<vscale x 1 x double> %b,
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i64 7, i64 %0)
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ret <vscale x 1 x double> %2
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}
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define <vscale x 1 x double> @intrinsic_diff_avl_reg(i64 %avl, i64 %avl2, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
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; CHECK-LABEL: intrinsic_diff_avl_reg:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmv1r.v v10, v9
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; CHECK-NEXT: vsetvli a0, a0, e64, m1, tu, ma
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; CHECK-NEXT: # implicit-def: $v9
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; CHECK-NEXT: vfadd.vv v9, v8, v10
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; CHECK-NEXT: vsetvli a0, a1, e64, m1, tu, ma
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; CHECK-NEXT: # implicit-def: $v8
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; CHECK-NEXT: vfadd.vv v8, v9, v10
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 7)
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%1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(
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<vscale x 1 x double> undef,
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<vscale x 1 x double> %a,
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<vscale x 1 x double> %b,
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i64 7, i64 %0)
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%2 = tail call i64 @llvm.riscv.vsetvli(i64 %avl2, i64 2, i64 7)
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%3 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(
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<vscale x 1 x double> undef,
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<vscale x 1 x double> %1,
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<vscale x 1 x double> %b,
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i64 7, i64 %2)
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ret <vscale x 1 x double> %3
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}

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