Skip to content

Commit d3e89f1

Browse files
dtcxzywdtcxzyw
committed
[InstCombine] Add pre-commit tests. NFC.
1 parent 848d7af commit d3e89f1

File tree

2 files changed

+181
-0
lines changed

2 files changed

+181
-0
lines changed

‎llvm/test/Transforms/InstCombine/switch-zext-sext.ll

Lines changed: 123 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,123 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
2+
; RUN: opt %s -passes=instcombine -S | FileCheck %s
3+
4+
define i1 @test_switch_with_zext(i16 %a, i1 %b, i1 %c) {
5+
; CHECK-LABEL: define i1 @test_switch_with_zext(
6+
; CHECK-SAME: i16 [[A:%.*]], i1 [[B:%.*]], i1 [[C:%.*]]) {
7+
; CHECK-NEXT: entry:
8+
; CHECK-NEXT: switch i16 [[A]], label [[SW_DEFAULT:%.*]] [
9+
; CHECK-NEXT: i16 37, label [[SW_BB:%.*]]
10+
; CHECK-NEXT: i16 38, label [[SW_BB]]
11+
; CHECK-NEXT: i16 39, label [[SW_BB]]
12+
; CHECK-NEXT: ]
13+
; CHECK: sw.bb:
14+
; CHECK-NEXT: ret i1 [[B]]
15+
; CHECK: sw.default:
16+
; CHECK-NEXT: ret i1 [[C]]
17+
;
18+
entry:
19+
%a.ext = zext i16 %a to i32
20+
switch i32 %a.ext, label %sw.default [
21+
i32 37, label %sw.bb
22+
i32 38, label %sw.bb
23+
i32 39, label %sw.bb
24+
]
25+
26+
sw.bb:
27+
ret i1 %b
28+
sw.default:
29+
ret i1 %c
30+
}
31+
32+
define i1 @test_switch_with_sext(i16 %a, i1 %b, i1 %c) {
33+
; CHECK-LABEL: define i1 @test_switch_with_sext(
34+
; CHECK-SAME: i16 [[A:%.*]], i1 [[B:%.*]], i1 [[C:%.*]]) {
35+
; CHECK-NEXT: entry:
36+
; CHECK-NEXT: [[A_EXT:%.*]] = sext i16 [[A]] to i32
37+
; CHECK-NEXT: switch i32 [[A_EXT]], label [[SW_DEFAULT:%.*]] [
38+
; CHECK-NEXT: i32 37, label [[SW_BB:%.*]]
39+
; CHECK-NEXT: i32 38, label [[SW_BB]]
40+
; CHECK-NEXT: i32 39, label [[SW_BB]]
41+
; CHECK-NEXT: ]
42+
; CHECK: sw.bb:
43+
; CHECK-NEXT: ret i1 [[B]]
44+
; CHECK: sw.default:
45+
; CHECK-NEXT: ret i1 [[C]]
46+
;
47+
entry:
48+
%a.ext = sext i16 %a to i32
49+
switch i32 %a.ext, label %sw.default [
50+
i32 37, label %sw.bb
51+
i32 38, label %sw.bb
52+
i32 39, label %sw.bb
53+
]
54+
55+
sw.bb:
56+
ret i1 %b
57+
sw.default:
58+
ret i1 %c
59+
}
60+
61+
; Negative tests
62+
63+
define i1 @test_switch_with_zext_unreachable_case(i16 %a, i1 %b, i1 %c) {
64+
; CHECK-LABEL: define i1 @test_switch_with_zext_unreachable_case(
65+
; CHECK-SAME: i16 [[A:%.*]], i1 [[B:%.*]], i1 [[C:%.*]]) {
66+
; CHECK-NEXT: entry:
67+
; CHECK-NEXT: [[A_EXT:%.*]] = zext i16 [[A]] to i32
68+
; CHECK-NEXT: switch i32 [[A_EXT]], label [[SW_DEFAULT:%.*]] [
69+
; CHECK-NEXT: i32 37, label [[SW_BB:%.*]]
70+
; CHECK-NEXT: i32 38, label [[SW_BB]]
71+
; CHECK-NEXT: i32 39, label [[SW_BB]]
72+
; CHECK-NEXT: i32 65537, label [[SW_BB]]
73+
; CHECK-NEXT: ]
74+
; CHECK: sw.bb:
75+
; CHECK-NEXT: ret i1 [[B]]
76+
; CHECK: sw.default:
77+
; CHECK-NEXT: ret i1 [[C]]
78+
;
79+
entry:
80+
%a.ext = zext i16 %a to i32
81+
switch i32 %a.ext, label %sw.default [
82+
i32 37, label %sw.bb
83+
i32 38, label %sw.bb
84+
i32 39, label %sw.bb
85+
i32 65537, label %sw.bb
86+
]
87+
88+
sw.bb:
89+
ret i1 %b
90+
sw.default:
91+
ret i1 %c
92+
}
93+
94+
define i1 @test_switch_with_sext_unreachable_case(i16 %a, i1 %b, i1 %c) {
95+
; CHECK-LABEL: define i1 @test_switch_with_sext_unreachable_case(
96+
; CHECK-SAME: i16 [[A:%.*]], i1 [[B:%.*]], i1 [[C:%.*]]) {
97+
; CHECK-NEXT: entry:
98+
; CHECK-NEXT: [[A_EXT:%.*]] = sext i16 [[A]] to i32
99+
; CHECK-NEXT: switch i32 [[A_EXT]], label [[SW_DEFAULT:%.*]] [
100+
; CHECK-NEXT: i32 37, label [[SW_BB:%.*]]
101+
; CHECK-NEXT: i32 38, label [[SW_BB]]
102+
; CHECK-NEXT: i32 39, label [[SW_BB]]
103+
; CHECK-NEXT: i32 -65537, label [[SW_BB]]
104+
; CHECK-NEXT: ]
105+
; CHECK: sw.bb:
106+
; CHECK-NEXT: ret i1 [[B]]
107+
; CHECK: sw.default:
108+
; CHECK-NEXT: ret i1 [[C]]
109+
;
110+
entry:
111+
%a.ext = sext i16 %a to i32
112+
switch i32 %a.ext, label %sw.default [
113+
i32 37, label %sw.bb
114+
i32 38, label %sw.bb
115+
i32 39, label %sw.bb
116+
i32 -65537, label %sw.bb
117+
]
118+
119+
sw.bb:
120+
ret i1 %b
121+
sw.default:
122+
ret i1 %c
123+
}

‎llvm/test/Transforms/PhaseOrdering/switch-sext.ll

Lines changed: 58 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,58 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
2+
; RUN: opt -S -passes='default<O3>' < %s | FileCheck %s
3+
4+
define i8 @test_switch_with_sext_phi(i8 %code) {
5+
; CHECK-LABEL: define i8 @test_switch_with_sext_phi(
6+
; CHECK-SAME: i8 [[CODE:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
7+
; CHECK-NEXT: entry:
8+
; CHECK-NEXT: [[CONV:%.*]] = sext i8 [[CODE]] to i32
9+
; CHECK-NEXT: switch i32 [[CONV]], label [[SW_DEFAULT:%.*]] [
10+
; CHECK-NEXT: i32 105, label [[SW_EPILOG:%.*]]
11+
; CHECK-NEXT: i32 73, label [[SW_BB1:%.*]]
12+
; CHECK-NEXT: i32 108, label [[SW_BB2:%.*]]
13+
; CHECK-NEXT: i32 76, label [[SW_BB3:%.*]]
14+
; CHECK-NEXT: i32 63, label [[SW_BB4:%.*]]
15+
; CHECK-NEXT: ]
16+
; CHECK: sw.bb1:
17+
; CHECK-NEXT: br label [[SW_EPILOG]]
18+
; CHECK: sw.bb2:
19+
; CHECK-NEXT: br label [[SW_EPILOG]]
20+
; CHECK: sw.bb3:
21+
; CHECK-NEXT: br label [[SW_EPILOG]]
22+
; CHECK: sw.bb4:
23+
; CHECK-NEXT: br label [[SW_EPILOG]]
24+
; CHECK: sw.default:
25+
; CHECK-NEXT: br label [[SW_EPILOG]]
26+
; CHECK: sw.epilog:
27+
; CHECK-NEXT: [[PEP_CODE:%.*]] = phi i8 [ [[CODE]], [[SW_DEFAULT]] ], [ 63, [[SW_BB4]] ], [ 81, [[SW_BB3]] ], [ 113, [[SW_BB2]] ], [ 73, [[SW_BB1]] ], [ 105, [[ENTRY:%.*]] ]
28+
; CHECK-NEXT: ret i8 [[PEP_CODE]]
29+
;
30+
entry:
31+
%conv = sext i8 %code to i32
32+
switch i32 %conv, label %sw.default [
33+
i32 105, label %sw.epilog
34+
i32 73, label %sw.bb1
35+
i32 108, label %sw.bb2
36+
i32 76, label %sw.bb3
37+
i32 63, label %sw.bb4
38+
]
39+
40+
sw.bb1:
41+
br label %sw.epilog
42+
43+
sw.bb2:
44+
br label %sw.epilog
45+
46+
sw.bb3:
47+
br label %sw.epilog
48+
49+
sw.bb4:
50+
br label %sw.epilog
51+
52+
sw.default:
53+
br label %sw.epilog
54+
55+
sw.epilog:
56+
%pep_code = phi i8 [ %code, %sw.default ], [ 63, %sw.bb4 ], [ 81, %sw.bb3 ], [ 113, %sw.bb2 ], [ 73, %sw.bb1 ], [ 105, %entry ]
57+
ret i8 %pep_code
58+
}

0 commit comments

Comments
 (0)