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[LLVM][AArch64] Add assembly/disassembly for MUL/BFMUL SME instructions (#113535)
According to https://developer.arm.com/documentation/ddi0602 Co-authored-by: Momchil-Velikov [email protected]
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‎llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

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@@ -1007,6 +1007,11 @@ let Predicates = [HasSME2p2] in {
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defm BFMOP4A : sme2_bfmop4as_widening<0, "bfmop4a">;
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defm BFMOP4S : sme2_bfmop4as_widening<1, "bfmop4s">;
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defm FMUL_2ZZ : sme2_multi2_fmul_sm<"fmul">;
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defm FMUL_2Z2Z : sme2_multi2_fmul_mm< "fmul">;
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defm FMUL_4ZZ : sme2_multi4_fmul_sm<"fmul">;
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defm FMUL_4Z4Z : sme2_multi4_fmul_mm< "fmul">;
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} // [HasSME2p2]
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let Predicates = [HasSME2p2, HasSMEB16B16] in {
@@ -1024,3 +1029,8 @@ let Predicates = [HasSME2p2, HasSMEF8F16], Uses = [FPMR, FPCR] in {
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let Predicates = [HasSME2p2, HasSMEF16F16] in {
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def FTMOPA_M2ZZZI_HtoH : sme_tmopa_16b<0b10001, ZZ_h_mul_r, ZPR16, "ftmopa">;
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} // [HasSME2p2, HasSMEF16F16]
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let Predicates = [HasSME2, HasSVEBFSCALE] in {
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defm BFMUL : sme2_bfmul_single<"bfmul">;
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defm BFMUL : sme2_bfmul_multi<"bfmul">;
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} //[HasSME2, HasSVEBFSCALE]

‎llvm/lib/Target/AArch64/SMEInstrFormats.td

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@@ -5225,3 +5225,113 @@ multiclass sme2_bfmop4as_widening<bit S, string mnemonic> {
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// Multiple vectors
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def _M2Z2Z_S : sme2_bf16_fp32_quarter_tile_outer_product<1, 1, S, mnemonic, ZZ_h_mul_r_Lo, ZZ_h_mul_r_Hi>;
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}
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class sme2_multi2_fmul_sm<bits<2> size, string mnemonic, RegisterOperand vector_ty, RegisterOperand zpr_ty>
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: I<(outs vector_ty:$Zd), (ins vector_ty:$Zn, zpr_ty:$Zm),
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mnemonic, "\t$Zd, $Zn, $Zm",
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"", []>, Sched<[]> {
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bits<4> Zd;
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bits<4> Zn;
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bits<4> Zm;
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let Inst{31-24} = 0b11000001;
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let Inst{23-22} = size;
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let Inst{21} = 0b1;
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let Inst{20-17} = Zm;
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let Inst{16-10} = 0b0111010;
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let Inst{9-6} = Zn;
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let Inst{5} = 0b0;
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let Inst{4-1} = Zd;
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let Inst{0} = 0b0;
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}
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multiclass sme2_multi2_fmul_sm<string mnemonic> {
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def _H : sme2_multi2_fmul_sm<0b01, mnemonic, ZZ_h_mul_r, ZPR4b16>;
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def _S : sme2_multi2_fmul_sm<0b10, mnemonic, ZZ_s_mul_r, ZPR4b32>;
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def _D : sme2_multi2_fmul_sm<0b11, mnemonic, ZZ_d_mul_r, ZPR4b64>;
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}
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class sme2_multi4_fmul_sm<bits<2> size, string mnemonic, RegisterOperand vector_ty, RegisterOperand zpr_ty>
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: I<(outs vector_ty:$Zd), (ins vector_ty:$Zn, zpr_ty:$Zm),
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mnemonic, "\t$Zd, $Zn, $Zm",
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"", []>, Sched<[]> {
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bits<3> Zd;
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bits<3> Zn;
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bits<4> Zm;
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let Inst{31-24} = 0b11000001;
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let Inst{23-22} = size;
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let Inst{21} = 0b1;
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let Inst{20-17} = Zm;
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let Inst{16-10} = 0b1111010;
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let Inst{9-7} = Zn;
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let Inst{6-5} = 0b00;
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let Inst{4-2} = Zd;
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let Inst{1-0} = 0b00;
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}
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multiclass sme2_multi4_fmul_sm<string mnemonic> {
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def _H : sme2_multi4_fmul_sm<0b01, mnemonic, ZZZZ_h_mul_r, ZPR4b16>;
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def _S : sme2_multi4_fmul_sm<0b10, mnemonic, ZZZZ_s_mul_r, ZPR4b32>;
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def _D : sme2_multi4_fmul_sm<0b11, mnemonic, ZZZZ_d_mul_r, ZPR4b64>;
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}
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multiclass sme2_bfmul_single<string mnemonic> {
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def _2ZZ : sme2_multi2_fmul_sm<0b00, mnemonic, ZZ_h_mul_r, ZPR4b16>;
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def _4ZZ : sme2_multi4_fmul_sm<0b00, mnemonic, ZZZZ_h_mul_r, ZPR4b16>;
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}
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class sme2_multi2_fmul_mm<bits<2> size, string mnemonic, RegisterOperand vector_ty>
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: I<(outs vector_ty:$Zd), (ins vector_ty:$Zn, vector_ty:$Zm),
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mnemonic, "\t$Zd, $Zn, $Zm",
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"", []>, Sched<[]> {
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bits<4> Zd;
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bits<4> Zn;
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bits<4> Zm;
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let Inst{31-24} = 0b11000001;
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let Inst{23-22} = size;
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let Inst{21} = 0b1;
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let Inst{20-17} = Zm;
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let Inst{16-10} = 0b0111001;
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let Inst{9-6} = Zn;
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let Inst{5} = 0b0;
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let Inst{4-1} = Zd;
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let Inst{0} = 0b0;
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}
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multiclass sme2_multi2_fmul_mm<string mnemonic> {
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def _H : sme2_multi2_fmul_mm<0b01, mnemonic, ZZ_h_mul_r>;
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def _S : sme2_multi2_fmul_mm<0b10, mnemonic, ZZ_s_mul_r>;
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def _D : sme2_multi2_fmul_mm<0b11, mnemonic, ZZ_d_mul_r>;
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}
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class sme2_multi4_fmul_mm<bits<2> size, string mnemonic, RegisterOperand vector_ty>
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: I<(outs vector_ty:$Zd), (ins vector_ty:$Zn, vector_ty:$Zm),
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mnemonic, "\t$Zd, $Zn, $Zm",
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"", []>, Sched<[]> {
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bits<3> Zd;
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bits<3> Zn;
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bits<3> Zm;
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let Inst{31-24} = 0b11000001;
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let Inst{23-22} = size;
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let Inst{21} = 0b1;
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let Inst{20-18} = Zm;
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let Inst{17-10} = 0b01111001;
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let Inst{9-7} = Zn;
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let Inst{6-5} = 0b00;
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let Inst{4-2} = Zd;
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let Inst{1-0} = 0b00;
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}
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multiclass sme2_multi4_fmul_mm<string mnemonic> {
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def _H : sme2_multi4_fmul_mm<0b01, mnemonic, ZZZZ_h_mul_r>;
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def _S : sme2_multi4_fmul_mm<0b10, mnemonic, ZZZZ_s_mul_r>;
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def _D : sme2_multi4_fmul_mm<0b11, mnemonic, ZZZZ_d_mul_r>;
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}
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multiclass sme2_bfmul_multi<string mnemonic> {
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def _2Z2Z : sme2_multi2_fmul_mm<0b00, mnemonic, ZZ_h_mul_r>;
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def _4Z4Z : sme2_multi4_fmul_mm<0b00, mnemonic, ZZZZ_h_mul_r>;
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}

‎llvm/test/MC/AArch64/SME2/bfmul-diagnostics.s

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// RUN: not llvm-mc -triple=aarch64 -mattr=+sme2,+sve-bfscale 2>&1 < %s| FileCheck %s
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// Multiple and single, 2 regs
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bfmul {z0.s-z1.s}, {z0.h-z1.h}, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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bfmul {z1.h-z2.h}, {z0.h-z1.h}, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
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bfmul {z0.h-z2.h}, {z0.h-z1.h}, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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bfmul {z0.h-z1.h}, {z0.s-z1.s}, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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bfmul {z0.h-z1.h}, {z1.h-z2.h}, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
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bfmul {z0.h-z1.h}, {z0.h-z2.h}, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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bfmul {z0.h-z1.h}, {z0.h-z1.h}, z0.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
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bfmul {z0.h-z1.h}, {z0.h-z1.h}, z16.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
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// Multiple and single, 4 regs
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bfmul {z0.s-z3.s}, {z0.h-z3.h}, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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bfmul {z1.h-z4.h}, {z0.h-z3.h}, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
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bfmul {z0.h-z4.h}, {z0.h-z3.h}, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
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bfmul {z0.h-z3.h}, {z0.s-z3.s}, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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bfmul {z0.h-z3.h}, {z1.h-z4.h}, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
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bfmul {z0.h-z3.h}, {z0.h-z4.h}, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
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bfmul {z0.h-z3.h}, {z0.h-z3.h}, z0.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
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bfmul {z0.h-z3.h}, {z0.h-z3.h}, z16.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
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// Multiple, 2 regs
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bfmul {z0.s-z1.s}, {z0.h-z1.h}, {z0.h-z1.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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bfmul {z1.h-z2.h}, {z0.h-z1.h}, {z0.h-z1.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
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bfmul {z0.h-z2.h}, {z0.h-z1.h}, {z0.h-z1.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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bfmul {z0.h-z1.h}, {z0.s-z1.s}, {z0.h-z1.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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bfmul {z0.h-z1.h}, {z1.h-z2.h}, {z0.h-z1.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
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bfmul {z0.h-z1.h}, {z0.h-z2.h}, {z0.h-z1.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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bfmul {z0.h-z1.h}, {z0.h-z1.h}, {z0.s-z1.s}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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bfmul {z0.h-z1.h}, {z0.h-z1.h}, {z1.h-z2.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
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bfmul {z0.h-z1.h}, {z0.h-z1.h}, {z0.h-z2.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// Multiple, 4 regs
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bfmul {z0.s-z3.s}, {z0.h-z3.h}, {z0.h-z3.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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bfmul {z1.h-z4.h}, {z0.h-z3.h}, {z0.h-z3.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
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bfmul {z0.h-z4.h}, {z0.h-z3.h}, {z0.h-z3.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
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bfmul {z0.h-z3.h}, {z0.s-z3.s}, {z0.h-z3.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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bfmul {z0.h-z3.h}, {z1.h-z4.h}, {z0.h-z3.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
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bfmul {z0.h-z3.h}, {z0.h-z4.h}, {z0.h-z3.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
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bfmul {z0.h-z3.h}, {z0.h-z3.h}, {z0.s-z3.s}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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bfmul {z0.h-z3.h}, {z0.h-z3.h}, {z1.h-z4.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
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bfmul {z0.h-z3.h}, {z0.h-z3.h}, {z0.h-z4.h}
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors

‎llvm/test/MC/AArch64/SME2/bfmul.s

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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sve-bfscale < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sve-bfscale < %s \
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// RUN: | llvm-objdump -d --mattr=+sme2,+sve-bfscale - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sve-bfscale < %s \
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// RUN: | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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// Disassemble encoding and check the re-encoding (-show-encoding) matches.
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sve-bfscale < %s \
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// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
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// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2,+sve-bfscale -disassemble -show-encoding \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// Multiple and single, 2 regs
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bfmul {z0.h-z1.h}, {z0.h-z1.h}, z0.h // 11000001-00100000-11101000-00000000
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// CHECK-INST: bfmul { z0.h, z1.h }, { z0.h, z1.h }, z0.h
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// CHECK-ENCODING: [0x00,0xe8,0x20,0xc1]
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// CHECK-ERROR: instruction requires: sme2 sve-bfscale
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// CHECK-UNKNOWN: c120e800 <unknown>
22+
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bfmul {z20.h-z21.h}, {z10.h-z11.h}, z10.h // 11000001-00110100-11101001-01010100
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// CHECK-INST: bfmul { z20.h, z21.h }, { z10.h, z11.h }, z10.h
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// CHECK-ENCODING: [0x54,0xe9,0x34,0xc1]
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// CHECK-ERROR: instruction requires: sme2 sve-bfscale
27+
// CHECK-UNKNOWN: c134e954 <unknown>
28+
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bfmul {z30.h-z31.h}, {z30.h-z31.h}, z15.h // 11000001-00111110-11101011-11011110
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// CHECK-INST: bfmul { z30.h, z31.h }, { z30.h, z31.h }, z15.h
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// CHECK-ENCODING: [0xde,0xeb,0x3e,0xc1]
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// CHECK-ERROR: instruction requires: sme2 sve-bfscale
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// CHECK-UNKNOWN: c13eebde <unknown>
34+
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// Multiple and single, 4 regs
36+
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bfmul {z0.h-z3.h}, {z0.h-z3.h}, z0.h // 11000001-00100001-11101000-00000000
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// CHECK-INST: bfmul { z0.h - z3.h }, { z0.h - z3.h }, z0.h
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// CHECK-ENCODING: [0x00,0xe8,0x21,0xc1]
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// CHECK-ERROR: instruction requires: sme2 sve-bfscale
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// CHECK-UNKNOWN: c121e800 <unknown>
42+
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bfmul {z20.h-z23.h}, {z8.h-z11.h}, z10.h // 11000001-00110101-11101001-00010100
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// CHECK-INST: bfmul { z20.h - z23.h }, { z8.h - z11.h }, z10.h
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// CHECK-ENCODING: [0x14,0xe9,0x35,0xc1]
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// CHECK-ERROR: instruction requires: sme2 sve-bfscale
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// CHECK-UNKNOWN: c135e914 <unknown>
48+
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bfmul {z28.h-z31.h}, {z28.h-z31.h}, z15.h // 11000001-00111111-11101011-10011100
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// CHECK-INST: bfmul { z28.h - z31.h }, { z28.h - z31.h }, z15.h
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// CHECK-ENCODING: [0x9c,0xeb,0x3f,0xc1]
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// CHECK-ERROR: instruction requires: sme2 sve-bfscale
53+
// CHECK-UNKNOWN: c13feb9c <unknown>
54+
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// Multiple, 2 regs
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bfmul {z0.h-z1.h}, {z0.h-z1.h}, {z0.h-z1.h} // 11000001-00100000-11100100-00000000
57+
// CHECK-INST: bfmul { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }
58+
// CHECK-ENCODING: [0x00,0xe4,0x20,0xc1]
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// CHECK-ERROR: instruction requires: sme2 sve-bfscale
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// CHECK-UNKNOWN: c120e400 <unknown>
61+
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bfmul {z20.h-z21.h}, {z10.h-z11.h}, {z20.h-z21.h} // 11000001-00110100-11100101-01010100
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// CHECK-INST: bfmul { z20.h, z21.h }, { z10.h, z11.h }, { z20.h, z21.h }
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// CHECK-ENCODING: [0x54,0xe5,0x34,0xc1]
65+
// CHECK-ERROR: instruction requires: sme2 sve-bfscale
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// CHECK-UNKNOWN: c134e554 <unknown>
67+
68+
bfmul {z30.h-z31.h}, {z30.h-z31.h}, {z30.h-z31.h} // 11000001-00111110-11100111-11011110
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// CHECK-INST: bfmul { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }
70+
// CHECK-ENCODING: [0xde,0xe7,0x3e,0xc1]
71+
// CHECK-ERROR: instruction requires: sme2 sve-bfscale
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// CHECK-UNKNOWN: c13ee7de <unknown>
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// Multiple, 4 regs
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bfmul {z0.h-z3.h}, {z0.h-z3.h}, {z0.h-z3.h} // 11000001-00100001-11100100-00000000
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// CHECK-INST: bfmul { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }
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// CHECK-ENCODING: [0x00,0xe4,0x21,0xc1]
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// CHECK-ERROR: instruction requires: sme2 sve-bfscale
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// CHECK-UNKNOWN: c121e400 <unknown>
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bfmul {z20.h-z23.h}, {z8.h-z11.h}, {z20.h-z23.h} // 11000001-00110101-11100101-00010100
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// CHECK-INST: bfmul { z20.h - z23.h }, { z8.h - z11.h }, { z20.h - z23.h }
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// CHECK-ENCODING: [0x14,0xe5,0x35,0xc1]
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// CHECK-ERROR: instruction requires: sme2 sve-bfscale
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// CHECK-UNKNOWN: c135e514 <unknown>
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bfmul {z28.h-z31.h}, {z28.h-z31.h}, {z28.h-z31.h} // 11000001-00111101-11100111-10011100
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// CHECK-INST: bfmul { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }
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// CHECK-ENCODING: [0x9c,0xe7,0x3d,0xc1]
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// CHECK-ERROR: instruction requires: sme2 sve-bfscale
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// CHECK-UNKNOWN: c13de79c <unknown>

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