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R600: Expand is_fpclass
Fixes #135083
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‎llvm/lib/Target/AMDGPU/R600ISelLowering.cpp

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Original file line numberDiff line numberDiff line change
@@ -100,6 +100,11 @@ R600TargetLowering::R600TargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::FSUB, MVT::f32, Expand);
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setOperationAction(ISD::IS_FPCLASS,
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{MVT::f32, MVT::v2f32, MVT::v3f32, MVT::v4f32, MVT::v5f32,
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MVT::v6f32, MVT::v7f32, MVT::v8f32, MVT::v16f32},
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Expand);
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setOperationAction({ISD::FCEIL, ISD::FTRUNC, ISD::FROUNDEVEN, ISD::FFLOOR},
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MVT::f64, Custom);
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‎llvm/test/CodeGen/AMDGPU/r600.llvm.is.fpclass.ll

Lines changed: 269 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=r600-- -mcpu=cayman < %s | FileCheck -check-prefix=CM %s
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define amdgpu_kernel void @isnan_f32(ptr addrspace(1) %out, float %x) {
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; CM-LABEL: isnan_f32:
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; CM: ; %bb.0:
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; CM-NEXT: ALU 6, @4, KC0[CB0:0-32], KC1[]
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; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
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; CM-NEXT: CF_END
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; CM-NEXT: PAD
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; CM-NEXT: ALU clause starting at 4:
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; CM-NEXT: AND_INT * T0.W, KC0[2].Z, literal.x,
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; CM-NEXT: 2147483647(nan), 0(0.000000e+00)
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; CM-NEXT: SETGT_INT * T0.W, PV.W, literal.x,
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; CM-NEXT: 2139095040(INF), 0(0.000000e+00)
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; CM-NEXT: AND_INT * T0.X, PV.W, 1,
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; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
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; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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%result = call i1 @llvm.is.fpclass.f32(float %x, i32 3) ; nan
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%zext = zext i1 %result to i32
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store i32 %zext, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_kernel void @issue135083_f32(ptr addrspace(1) %out, float %x) {
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; CM-LABEL: issue135083_f32:
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; CM: ; %bb.0:
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; CM-NEXT: ALU 6, @4, KC0[CB0:0-32], KC1[]
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; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
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; CM-NEXT: CF_END
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; CM-NEXT: PAD
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; CM-NEXT: ALU clause starting at 4:
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; CM-NEXT: AND_INT * T0.W, KC0[2].Z, literal.x,
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; CM-NEXT: 2147483647(nan), 0(0.000000e+00)
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; CM-NEXT: SETGT_INT * T0.W, literal.x, PV.W,
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; CM-NEXT: 2139095040(INF), 0(0.000000e+00)
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; CM-NEXT: AND_INT * T0.X, PV.W, 1,
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; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
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; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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%result = call i1 @llvm.is.fpclass.f32(float %x, i32 504)
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%zext = zext i1 %result to i32
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store i32 %zext, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_kernel void @issue135083_v2f32(ptr addrspace(1) %out, <2 x float> %x) {
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; CM-LABEL: issue135083_v2f32:
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; CM: ; %bb.0:
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; CM-NEXT: ALU 10, @4, KC0[CB0:0-32], KC1[]
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; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X
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; CM-NEXT: CF_END
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; CM-NEXT: PAD
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; CM-NEXT: ALU clause starting at 4:
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; CM-NEXT: AND_INT * T0.W, KC0[3].X, literal.x,
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; CM-NEXT: 2147483647(nan), 0(0.000000e+00)
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; CM-NEXT: AND_INT T0.Z, KC0[2].W, literal.x,
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; CM-NEXT: SETGT_INT * T0.W, PV.W, literal.y,
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; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)
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; CM-NEXT: CNDE_INT T0.Y, PV.W, 1, 0.0,
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; CM-NEXT: SETGT_INT * T0.W, PV.Z, literal.x,
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; CM-NEXT: 2139095039(3.402823e+38), 0(0.000000e+00)
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; CM-NEXT: CNDE_INT * T0.X, PV.W, 1, 0.0,
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; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
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; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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%result = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, i32 504)
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%zext = zext <2 x i1> %result to <2 x i32>
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store <2 x i32> %zext, ptr addrspace(1) %out, align 8
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ret void
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}
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define amdgpu_kernel void @issue135083_v3f32(ptr addrspace(1) %out, <3 x float> %x) {
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; CM-LABEL: issue135083_v3f32:
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; CM: ; %bb.0:
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; CM-NEXT: ALU 17, @4, KC0[CB0:0-32], KC1[]
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; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2, T3.X
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; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
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; CM-NEXT: CF_END
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; CM-NEXT: ALU clause starting at 4:
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; CM-NEXT: AND_INT * T0.W, KC0[3].W, literal.x,
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; CM-NEXT: 2147483647(nan), 0(0.000000e+00)
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; CM-NEXT: AND_INT T0.Z, KC0[3].Z, literal.x,
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; CM-NEXT: SETGT_INT * T0.W, PV.W, literal.y,
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; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)
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; CM-NEXT: CNDE_INT T0.X, PV.W, 1, 0.0,
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; CM-NEXT: AND_INT T0.Y, KC0[3].Y, literal.x,
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; CM-NEXT: SETGT_INT T0.Z, PV.Z, literal.y,
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; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z,
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; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)
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; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)
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; CM-NEXT: LSHR T1.X, PV.W, literal.x,
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; CM-NEXT: CNDE_INT T2.Y, PV.Z, 1, 0.0,
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; CM-NEXT: SETGT_INT * T0.W, PV.Y, literal.y,
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; CM-NEXT: 2(2.802597e-45), 2139095039(3.402823e+38)
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; CM-NEXT: CNDE_INT * T2.X, PV.W, 1, 0.0,
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; CM-NEXT: LSHR * T3.X, KC0[2].Y, literal.x,
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; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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%result = call <3 x i1> @llvm.is.fpclass.v3f32(<3 x float> %x, i32 504)
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%zext = zext <3 x i1> %result to <3 x i32>
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store <3 x i32> %zext, ptr addrspace(1) %out, align 16
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ret void
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}
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define amdgpu_kernel void @issue135083_v4f32(ptr addrspace(1) %out, <4 x float> %x) {
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; CM-LABEL: issue135083_v4f32:
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; CM: ; %bb.0:
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; CM-NEXT: ALU 18, @4, KC0[CB0:0-32], KC1[]
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; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X
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; CM-NEXT: CF_END
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; CM-NEXT: PAD
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; CM-NEXT: ALU clause starting at 4:
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; CM-NEXT: AND_INT * T0.W, KC0[4].X, literal.x,
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; CM-NEXT: 2147483647(nan), 0(0.000000e+00)
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; CM-NEXT: SETGT_INT T0.Z, PV.W, literal.x,
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; CM-NEXT: AND_INT * T0.W, KC0[3].W, literal.y,
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; CM-NEXT: 2139095039(3.402823e+38), 2147483647(nan)
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; CM-NEXT: AND_INT T0.Y, KC0[3].Z, literal.x,
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; CM-NEXT: SETGT_INT T1.Z, PV.W, literal.y,
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; CM-NEXT: CNDE_INT * T0.W, PV.Z, 1, 0.0,
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; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)
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; CM-NEXT: AND_INT T1.Y, KC0[3].Y, literal.x,
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; CM-NEXT: CNDE_INT T0.Z, PV.Z, 1, 0.0,
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; CM-NEXT: SETGT_INT * T1.W, PV.Y, literal.y,
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; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)
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; CM-NEXT: CNDE_INT T0.Y, PV.W, 1, 0.0,
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; CM-NEXT: SETGT_INT * T1.W, PV.Y, literal.x,
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; CM-NEXT: 2139095039(3.402823e+38), 0(0.000000e+00)
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; CM-NEXT: CNDE_INT * T0.X, PV.W, 1, 0.0,
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; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
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; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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%result = call <4 x i1> @llvm.is.fpclass.v3f32(<4 x float> %x, i32 504)
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%zext = zext <4 x i1> %result to <4 x i32>
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store <4 x i32> %zext, ptr addrspace(1) %out, align 16
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ret void
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}
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define amdgpu_kernel void @issue135083_v8f32(ptr addrspace(1) %out, <8 x float> %x) {
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; CM-LABEL: issue135083_v8f32:
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; CM: ; %bb.0:
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; CM-NEXT: ALU 34, @4, KC0[CB0:0-32], KC1[]
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; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T3.X
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; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1, T2.X
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; CM-NEXT: CF_END
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; CM-NEXT: ALU clause starting at 4:
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; CM-NEXT: AND_INT T0.Z, KC0[6].X, literal.x,
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; CM-NEXT: AND_INT * T0.W, KC0[4].W, literal.x,
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; CM-NEXT: 2147483647(nan), 0(0.000000e+00)
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; CM-NEXT: AND_INT T0.X, KC0[4].Y, literal.x,
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; CM-NEXT: SETGT_INT T0.Y, PV.W, literal.y,
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; CM-NEXT: SETGT_INT T0.Z, PV.Z, literal.y,
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; CM-NEXT: AND_INT * T0.W, KC0[5].W, literal.x,
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; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)
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; CM-NEXT: AND_INT T1.X, KC0[5].Z, literal.x,
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; CM-NEXT: SETGT_INT T1.Y, PV.W, literal.y,
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; CM-NEXT: AND_INT T1.Z, KC0[5].X, literal.x,
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; CM-NEXT: CNDE_INT * T1.W, PV.Z, 1, 0.0,
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; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)
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; CM-NEXT: SETGT_INT T2.X, PV.Z, literal.x,
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; CM-NEXT: AND_INT T2.Y, KC0[5].Y, literal.y,
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; CM-NEXT: CNDE_INT T1.Z, PV.Y, 1, 0.0,
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; CM-NEXT: SETGT_INT * T0.W, PV.X, literal.x,
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; CM-NEXT: 2139095039(3.402823e+38), 2147483647(nan)
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; CM-NEXT: AND_INT T3.X, KC0[4].Z, literal.x,
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; CM-NEXT: CNDE_INT T1.Y, PV.W, 1, 0.0,
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; CM-NEXT: SETGT_INT T0.Z, PV.Y, literal.y,
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; CM-NEXT: CNDE_INT * T0.W, PV.X, 1, 0.0,
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; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)
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; CM-NEXT: CNDE_INT T1.X, PV.Z, 1, 0.0,
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; CM-NEXT: SETGT_INT T2.Y, PV.X, literal.x,
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; CM-NEXT: CNDE_INT T0.Z, T0.Y, 1, 0.0,
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; CM-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.y,
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; CM-NEXT: 2139095039(3.402823e+38), 16(2.242078e-44)
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; CM-NEXT: LSHR T2.X, PV.W, literal.x,
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; CM-NEXT: CNDE_INT T0.Y, PV.Y, 1, 0.0,
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; CM-NEXT: SETGT_INT * T2.W, T0.X, literal.y,
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; CM-NEXT: 2(2.802597e-45), 2139095039(3.402823e+38)
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; CM-NEXT: CNDE_INT * T0.X, PV.W, 1, 0.0,
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; CM-NEXT: LSHR * T3.X, KC0[2].Y, literal.x,
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; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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%result = call <8 x i1> @llvm.is.fpclass.v3f32(<8 x float> %x, i32 504)
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%zext = zext <8 x i1> %result to <8 x i32>
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store <8 x i32> %zext, ptr addrspace(1) %out, align 32
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ret void
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}
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define amdgpu_kernel void @issue135083_v16f32(ptr addrspace(1) %out, <16 x float> %x) {
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; CM-LABEL: issue135083_v16f32:
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; CM: ; %bb.0:
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; CM-NEXT: ALU 69, @6, KC0[CB0:0-32], KC1[]
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; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1, T7.X
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; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2, T0.X
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; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T3, T6.X
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; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T4, T5.X
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; CM-NEXT: CF_END
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; CM-NEXT: ALU clause starting at 6:
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; CM-NEXT: AND_INT T0.Z, KC0[6].Y, literal.x,
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; CM-NEXT: AND_INT * T0.W, KC0[6].W, literal.x,
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; CM-NEXT: 2147483647(nan), 0(0.000000e+00)
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; CM-NEXT: SETGT_INT T0.X, PV.W, literal.x,
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; CM-NEXT: AND_INT T0.Y, KC0[6].Z, literal.y,
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; CM-NEXT: AND_INT T1.Z, KC0[7].Y, literal.y,
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; CM-NEXT: AND_INT * T0.W, KC0[7].X, literal.y,
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; CM-NEXT: 2139095039(3.402823e+38), 2147483647(nan)
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; CM-NEXT: SETGT_INT T1.X, PV.W, literal.x,
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; CM-NEXT: AND_INT T1.Y, KC0[7].Z, literal.y,
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; CM-NEXT: AND_INT T2.Z, KC0[8].X, literal.y,
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; CM-NEXT: AND_INT * T0.W, KC0[7].W, literal.y,
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; CM-NEXT: 2139095039(3.402823e+38), 2147483647(nan)
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; CM-NEXT: SETGT_INT T2.X, PV.W, literal.x,
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; CM-NEXT: SETGT_INT T2.Y, PV.Z, literal.x,
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; CM-NEXT: AND_INT T2.Z, KC0[10].X, literal.y,
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; CM-NEXT: AND_INT * T0.W, KC0[8].W, literal.y,
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; CM-NEXT: 2139095039(3.402823e+38), 2147483647(nan)
213+
; CM-NEXT: AND_INT T3.X, KC0[8].Y, literal.x,
214+
; CM-NEXT: SETGT_INT T3.Y, PV.W, literal.y,
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; CM-NEXT: SETGT_INT T2.Z, PV.Z, literal.y,
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; CM-NEXT: AND_INT * T0.W, KC0[9].W, literal.x,
217+
; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)
218+
; CM-NEXT: AND_INT T4.X, KC0[9].Z, literal.x,
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; CM-NEXT: SETGT_INT T4.Y, PV.W, literal.y,
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; CM-NEXT: AND_INT T3.Z, KC0[9].X, literal.x,
221+
; CM-NEXT: CNDE_INT * T4.W, PV.Z, 1, 0.0,
222+
; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)
223+
; CM-NEXT: SETGT_INT T5.X, PV.Z, literal.x,
224+
; CM-NEXT: AND_INT T5.Y, KC0[9].Y, literal.y,
225+
; CM-NEXT: CNDE_INT T4.Z, PV.Y, 1, 0.0,
226+
; CM-NEXT: SETGT_INT * T0.W, PV.X, literal.x,
227+
; CM-NEXT: 2139095039(3.402823e+38), 2147483647(nan)
228+
; CM-NEXT: AND_INT T6.X, KC0[8].Z, literal.x,
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; CM-NEXT: CNDE_INT T4.Y, PV.W, 1, 0.0,
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; CM-NEXT: SETGT_INT T2.Z, PV.Y, literal.y,
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; CM-NEXT: CNDE_INT * T3.W, PV.X, 1, 0.0,
232+
; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)
233+
; CM-NEXT: CNDE_INT T4.X, PV.Z, 1, 0.0,
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; CM-NEXT: SETGT_INT T5.Y, PV.X, literal.x,
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; CM-NEXT: CNDE_INT T3.Z, T3.Y, 1, 0.0,
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; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
237+
; CM-NEXT: 2139095039(3.402823e+38), 48(6.726233e-44)
238+
; CM-NEXT: LSHR T5.X, PV.W, literal.x,
239+
; CM-NEXT: CNDE_INT T3.Y, PV.Y, 1, 0.0,
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; CM-NEXT: SETGT_INT T2.Z, T3.X, literal.y,
241+
; CM-NEXT: CNDE_INT * T2.W, T2.Y, 1, 0.0,
242+
; CM-NEXT: 2(2.802597e-45), 2139095039(3.402823e+38)
243+
; CM-NEXT: CNDE_INT T3.X, PV.Z, 1, 0.0,
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; CM-NEXT: SETGT_INT T1.Y, T1.Y, literal.x,
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; CM-NEXT: CNDE_INT T2.Z, T2.X, 1, 0.0,
246+
; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
247+
; CM-NEXT: 2139095039(3.402823e+38), 32(4.484155e-44)
248+
; CM-NEXT: LSHR T6.X, PV.W, literal.x,
249+
; CM-NEXT: CNDE_INT T2.Y, PV.Y, 1, 0.0,
250+
; CM-NEXT: SETGT_INT T1.Z, T1.Z, literal.y,
251+
; CM-NEXT: CNDE_INT * T1.W, T1.X, 1, 0.0,
252+
; CM-NEXT: 2(2.802597e-45), 2139095039(3.402823e+38)
253+
; CM-NEXT: CNDE_INT T2.X, PV.Z, 1, 0.0,
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; CM-NEXT: SETGT_INT T0.Y, T0.Y, literal.x,
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; CM-NEXT: CNDE_INT T1.Z, T0.X, 1, 0.0,
256+
; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
257+
; CM-NEXT: 2139095039(3.402823e+38), 16(2.242078e-44)
258+
; CM-NEXT: LSHR T0.X, PV.W, literal.x,
259+
; CM-NEXT: CNDE_INT T1.Y, PV.Y, 1, 0.0,
260+
; CM-NEXT: SETGT_INT * T0.W, T0.Z, literal.y,
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; CM-NEXT: 2(2.802597e-45), 2139095039(3.402823e+38)
262+
; CM-NEXT: CNDE_INT * T1.X, PV.W, 1, 0.0,
263+
; CM-NEXT: LSHR * T7.X, KC0[2].Y, literal.x,
264+
; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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%result = call <16 x i1> @llvm.is.fpclass.v3f32(<16 x float> %x, i32 504)
266+
%zext = zext <16 x i1> %result to <16 x i32>
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store <16 x i32> %zext, ptr addrspace(1) %out, align 64
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ret void
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}

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