We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent f3fd1ec commit d473e2cCopy full SHA for d473e2c
llvm/test/tools/llvm-mca/RISCV/SiFive7/strided-load-x0.s
@@ -1,5 +1,5 @@
1
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
2
-# RUN: llvm-mca -debug -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s | FileCheck %s
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s | FileCheck %s
3
4
vsetvli zero, zero, e32, m1, tu, mu
5
0 commit comments