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davemgreendavemgreen
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[AArch64][GlobalISel] Selection for i8 buildvectors
Legalization for i8 buildvectors is available (as in 615695d), but selection would fail due to i8 types not being handled. This adds basic support like other type sizes. Differential Revision: https://reviews.llvm.org/D143002
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‎llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3994,6 +3994,8 @@ MachineInstr *AArch64InstructionSelector::emitScalarToVector(
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};
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switch (EltSize) {
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case 8:
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return BuildFn(AArch64::bsub);
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case 16:
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return BuildFn(AArch64::hsub);
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case 32:
@@ -5543,7 +5545,7 @@ bool AArch64InstructionSelector::selectBuildVector(MachineInstr &I,
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if (tryOptBuildVecToSubregToReg(I, MRI))
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return true;
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5546-
if (EltSize < 16 || EltSize > 64)
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if (EltSize != 8 && EltSize != 16 && EltSize != 32 && EltSize != 64)
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return false; // Don't support all element types yet.
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const RegisterBank &RB = *RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI);
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‎llvm/test/CodeGen/AArch64/GlobalISel/select-unmerge.mir

Lines changed: 85 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -308,6 +308,91 @@ body: |
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RET_ReallyLR implicit $d0
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...
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---
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name: test_v16s8_unmerge
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $q0
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; CHECK-LABEL: name: test_v16s8_unmerge
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; CHECK: liveins: $q0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr8 = COPY [[COPY]].bsub
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; CHECK-NEXT: [[DUPi8_:%[0-9]+]]:fpr8 = DUPi8 [[COPY]], 1
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; CHECK-NEXT: [[DUPi8_1:%[0-9]+]]:fpr8 = DUPi8 [[COPY]], 2
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; CHECK-NEXT: [[DUPi8_2:%[0-9]+]]:fpr8 = DUPi8 [[COPY]], 3
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; CHECK-NEXT: [[DUPi8_3:%[0-9]+]]:fpr8 = DUPi8 [[COPY]], 4
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; CHECK-NEXT: [[DUPi8_4:%[0-9]+]]:fpr8 = DUPi8 [[COPY]], 5
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; CHECK-NEXT: [[DUPi8_5:%[0-9]+]]:fpr8 = DUPi8 [[COPY]], 6
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; CHECK-NEXT: [[DUPi8_6:%[0-9]+]]:fpr8 = DUPi8 [[COPY]], 7
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; CHECK-NEXT: [[DUPi8_7:%[0-9]+]]:fpr8 = DUPi8 [[COPY]], 8
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; CHECK-NEXT: [[DUPi8_8:%[0-9]+]]:fpr8 = DUPi8 [[COPY]], 9
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; CHECK-NEXT: [[DUPi8_9:%[0-9]+]]:fpr8 = DUPi8 [[COPY]], 10
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; CHECK-NEXT: [[DUPi8_10:%[0-9]+]]:fpr8 = DUPi8 [[COPY]], 11
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; CHECK-NEXT: [[DUPi8_11:%[0-9]+]]:fpr8 = DUPi8 [[COPY]], 12
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; CHECK-NEXT: [[DUPi8_12:%[0-9]+]]:fpr8 = DUPi8 [[COPY]], 13
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; CHECK-NEXT: [[DUPi8_13:%[0-9]+]]:fpr8 = DUPi8 [[COPY]], 14
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; CHECK-NEXT: [[DUPi8_14:%[0-9]+]]:fpr8 = DUPi8 [[COPY]], 15
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; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.bsub
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; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[DUPi8_]], %subreg.bsub
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; CHECK-NEXT: [[INSvi8lane:%[0-9]+]]:fpr128 = INSvi8lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
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; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[DUPi8_1]], %subreg.bsub
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; CHECK-NEXT: [[INSvi8lane1:%[0-9]+]]:fpr128 = INSvi8lane [[INSvi8lane]], 2, [[INSERT_SUBREG2]], 0
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; CHECK-NEXT: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[DUPi8_2]], %subreg.bsub
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; CHECK-NEXT: [[INSvi8lane2:%[0-9]+]]:fpr128 = INSvi8lane [[INSvi8lane1]], 3, [[INSERT_SUBREG3]], 0
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; CHECK-NEXT: [[DEF4:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF4]], [[DUPi8_3]], %subreg.bsub
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; CHECK-NEXT: [[INSvi8lane3:%[0-9]+]]:fpr128 = INSvi8lane [[INSvi8lane2]], 4, [[INSERT_SUBREG4]], 0
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; CHECK-NEXT: [[DEF5:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF5]], [[DUPi8_4]], %subreg.bsub
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; CHECK-NEXT: [[INSvi8lane4:%[0-9]+]]:fpr128 = INSvi8lane [[INSvi8lane3]], 5, [[INSERT_SUBREG5]], 0
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; CHECK-NEXT: [[DEF6:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[INSERT_SUBREG6:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF6]], [[DUPi8_5]], %subreg.bsub
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; CHECK-NEXT: [[INSvi8lane5:%[0-9]+]]:fpr128 = INSvi8lane [[INSvi8lane4]], 6, [[INSERT_SUBREG6]], 0
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; CHECK-NEXT: [[DEF7:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[INSERT_SUBREG7:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF7]], [[DUPi8_6]], %subreg.bsub
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; CHECK-NEXT: [[INSvi8lane6:%[0-9]+]]:fpr128 = INSvi8lane [[INSvi8lane5]], 7, [[INSERT_SUBREG7]], 0
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; CHECK-NEXT: [[DEF8:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[INSERT_SUBREG8:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF8]], [[DUPi8_7]], %subreg.bsub
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; CHECK-NEXT: [[INSvi8lane7:%[0-9]+]]:fpr128 = INSvi8lane [[INSvi8lane6]], 8, [[INSERT_SUBREG8]], 0
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; CHECK-NEXT: [[DEF9:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[INSERT_SUBREG9:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF9]], [[DUPi8_8]], %subreg.bsub
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; CHECK-NEXT: [[INSvi8lane8:%[0-9]+]]:fpr128 = INSvi8lane [[INSvi8lane7]], 9, [[INSERT_SUBREG9]], 0
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; CHECK-NEXT: [[DEF10:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[INSERT_SUBREG10:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF10]], [[DUPi8_9]], %subreg.bsub
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; CHECK-NEXT: [[INSvi8lane9:%[0-9]+]]:fpr128 = INSvi8lane [[INSvi8lane8]], 10, [[INSERT_SUBREG10]], 0
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; CHECK-NEXT: [[DEF11:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[INSERT_SUBREG11:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF11]], [[DUPi8_10]], %subreg.bsub
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; CHECK-NEXT: [[INSvi8lane10:%[0-9]+]]:fpr128 = INSvi8lane [[INSvi8lane9]], 11, [[INSERT_SUBREG11]], 0
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; CHECK-NEXT: [[DEF12:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[INSERT_SUBREG12:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF12]], [[DUPi8_11]], %subreg.bsub
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; CHECK-NEXT: [[INSvi8lane11:%[0-9]+]]:fpr128 = INSvi8lane [[INSvi8lane10]], 12, [[INSERT_SUBREG12]], 0
377+
; CHECK-NEXT: [[DEF13:%[0-9]+]]:fpr128 = IMPLICIT_DEF
378+
; CHECK-NEXT: [[INSERT_SUBREG13:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF13]], [[DUPi8_12]], %subreg.bsub
379+
; CHECK-NEXT: [[INSvi8lane12:%[0-9]+]]:fpr128 = INSvi8lane [[INSvi8lane11]], 13, [[INSERT_SUBREG13]], 0
380+
; CHECK-NEXT: [[DEF14:%[0-9]+]]:fpr128 = IMPLICIT_DEF
381+
; CHECK-NEXT: [[INSERT_SUBREG14:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF14]], [[DUPi8_13]], %subreg.bsub
382+
; CHECK-NEXT: [[INSvi8lane13:%[0-9]+]]:fpr128 = INSvi8lane [[INSvi8lane12]], 14, [[INSERT_SUBREG14]], 0
383+
; CHECK-NEXT: [[DEF15:%[0-9]+]]:fpr128 = IMPLICIT_DEF
384+
; CHECK-NEXT: [[INSERT_SUBREG15:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF15]], [[DUPi8_14]], %subreg.bsub
385+
; CHECK-NEXT: [[INSvi8lane14:%[0-9]+]]:fpr128 = INSvi8lane [[INSvi8lane13]], 15, [[INSERT_SUBREG15]], 0
386+
; CHECK-NEXT: $q0 = COPY [[INSvi8lane14]]
387+
; CHECK-NEXT: RET_ReallyLR implicit $q0
388+
%0:fpr(<16 x s8>) = COPY $q0
389+
%2:fpr(s8), %3:fpr(s8), %4:fpr(s8), %5:fpr(s8), %6:fpr(s8), %7:fpr(s8), %8:fpr(s8), %9:fpr(s8), %10:fpr(s8), %11:fpr(s8), %12:fpr(s8), %13:fpr(s8), %14:fpr(s8), %15:fpr(s8), %16:fpr(s8), %17:fpr(s8) = G_UNMERGE_VALUES %0(<16 x s8>)
390+
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%1:fpr(<16 x s8>) = G_BUILD_VECTOR %2:fpr(s8), %3:fpr(s8), %4:fpr(s8), %5:fpr(s8), %6:fpr(s8), %7:fpr(s8), %8:fpr(s8), %9:fpr(s8), %10:fpr(s8), %11:fpr(s8), %12:fpr(s8), %13:fpr(s8), %14:fpr(s8), %15:fpr(s8), %16:fpr(s8), %17:fpr(s8)
392+
$q0 = COPY %1(<16 x s8>)
393+
RET_ReallyLR implicit $q0
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...
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---
311396
name: test_vecsplit_2v2s32_v4s32
312397
alignment: 4
313398
legalized: true

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