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1 parent 9860fd0 commit d532ee6Copy full SHA for d532ee6
mlir/test/Integration/Dialect/SparseTensor/CPU/concatenate_dim_0_permute.mlir
@@ -153,7 +153,7 @@ module {
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//
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%4 = call @concat_sparse_sparse_perm(%sm24ccp, %sm34cd, %sm44dc)
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: (tensor<2x4xf64, #MAT_C_C_P>, tensor<3x4xf64, #MAT_C_D>, tensor<4x4xf64, #MAT_D_C>) -> tensor<9x4xf64, #MAT_C_C_P>
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- sparse_tensor.print %4 : tensor<9x4xf64, #MAT_C_C_P>
+ sparse_tensor.print %4 : tensor<9x4xf64, #MAT_C_C_P>
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// CHECK: {{\[}}[1, 0, 3, 0],
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// CHECK-NEXT: [0, 2, 0, 0],
@@ -182,7 +182,7 @@ module {
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%6 = call @concat_mix_sparse_perm(%m24, %sm34cdp, %sm44dc)
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: (tensor<2x4xf64>, tensor<3x4xf64, #MAT_C_D_P>, tensor<4x4xf64, #MAT_D_C>) -> tensor<9x4xf64, #MAT_C_C>
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- sparse_tensor.print %6 : tensor<9x4xf64, #MAT_C_C>
+ sparse_tensor.print %6 : tensor<9x4xf64, #MAT_C_C>
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