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[RISCV][test] Precommit test for non-power-of-2 VLS type code gen
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‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-non-power-of-2.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
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; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
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define void @vls3i8(ptr align 8 %array) {
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; CHECK-LABEL: vls3i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vadd.vv v8, v8, v8
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; CHECK-NEXT: vsetivli zero, 3, e8, mf4, ta, ma
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; CHECK-NEXT: vse8.v v8, (a0)
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; CHECK-NEXT: ret
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entry:
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%arr = getelementptr inbounds <3 x i8>, ptr %array, i64 0
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%1 = load <3 x i8>, ptr %array, align 1
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%2 = add<3 x i8> %1, %1
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store <3 x i8> %2, ptr %array, align 1
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ret void
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}
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define void @vls3(ptr align 8 %array) {
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; CHECK-LABEL: vls3:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 3, e32, m1, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0)
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vadd.vv v8, v8, v8
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; CHECK-NEXT: vsetivli zero, 3, e32, m1, ta, ma
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; CHECK-NEXT: vse32.v v8, (a0)
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; CHECK-NEXT: ret
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entry:
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%arr = getelementptr inbounds <3 x i32>, ptr %array, i64 0
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%1 = load <3 x i32>, ptr %array, align 4
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%2 = add<3 x i32> %1, %1
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store <3 x i32> %2, ptr %array, align 4
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ret void
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}
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define void @vls5(ptr align 8 %array) {
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; CHECK-LABEL: vls5:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 5, e32, m2, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0)
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; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
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; CHECK-NEXT: vadd.vv v8, v8, v8
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; CHECK-NEXT: vsetivli zero, 5, e32, m2, ta, ma
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; CHECK-NEXT: vse32.v v8, (a0)
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; CHECK-NEXT: ret
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entry:
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%arr = getelementptr inbounds <5 x i32>, ptr %array, i64 0
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%1 = load <5 x i32>, ptr %array, align 4
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%2 = add<5 x i32> %1, %1
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store <5 x i32> %2, ptr %array, align 4
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ret void
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}
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define void @vls6(ptr align 8 %array) {
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; CHECK-LABEL: vls6:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0)
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; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
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; CHECK-NEXT: vadd.vv v8, v8, v8
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; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma
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; CHECK-NEXT: vse32.v v8, (a0)
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; CHECK-NEXT: ret
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entry:
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%arr = getelementptr inbounds <6 x i32>, ptr %array, i64 0
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%1 = load <6 x i32>, ptr %array, align 4
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%2 = add<6 x i32> %1, %1
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store <6 x i32> %2, ptr %array, align 4
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ret void
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}
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define void @vls7(ptr align 8 %array) {
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; CHECK-LABEL: vls7:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0)
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; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
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; CHECK-NEXT: vadd.vv v8, v8, v8
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; CHECK-NEXT: vsetivli zero, 7, e32, m2, ta, ma
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; CHECK-NEXT: vse32.v v8, (a0)
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; CHECK-NEXT: ret
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entry:
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%arr = getelementptr inbounds <7 x i32>, ptr %array, i64 0
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%1 = load <7 x i32>, ptr %array, align 4
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%2 = add<7 x i32> %1, %1
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store <7 x i32> %2, ptr %array, align 4
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ret void
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}
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define void @vls9(ptr align 8 %array) {
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; CHECK-LABEL: vls9:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 9, e32, m4, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0)
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; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
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; CHECK-NEXT: vadd.vv v8, v8, v8
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; CHECK-NEXT: vsetivli zero, 9, e32, m4, ta, ma
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; CHECK-NEXT: vse32.v v8, (a0)
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; CHECK-NEXT: ret
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entry:
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%arr = getelementptr inbounds <9 x i32>, ptr %array, i64 0
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%1 = load <9 x i32>, ptr %array, align 4
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%2 = add<9 x i32> %1, %1
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store <9 x i32> %2, ptr %array, align 4
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ret void
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}
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define void @vls10(ptr align 8 %array) {
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; CHECK-LABEL: vls10:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 10, e32, m4, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0)
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; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
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; CHECK-NEXT: vadd.vv v8, v8, v8
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; CHECK-NEXT: vsetivli zero, 10, e32, m4, ta, ma
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; CHECK-NEXT: vse32.v v8, (a0)
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; CHECK-NEXT: ret
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entry:
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%arr = getelementptr inbounds <10 x i32>, ptr %array, i64 0
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%1 = load <10 x i32>, ptr %array, align 4
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%2 = add<10 x i32> %1, %1
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store <10 x i32> %2, ptr %array, align 4
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ret void
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}
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define void @vls11(ptr align 8 %array) {
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; CHECK-LABEL: vls11:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 11, e32, m4, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0)
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; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
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; CHECK-NEXT: vadd.vv v8, v8, v8
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; CHECK-NEXT: vsetivli zero, 11, e32, m4, ta, ma
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; CHECK-NEXT: vse32.v v8, (a0)
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; CHECK-NEXT: ret
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entry:
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%arr = getelementptr inbounds <11 x i32>, ptr %array, i64 0
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%1 = load <11 x i32>, ptr %array, align 4
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%2 = add<11 x i32> %1, %1
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store <11 x i32> %2, ptr %array, align 4
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ret void
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}

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