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[RISCV] Add Syntacore SCR3 processor definition (#95953)
Syntacore SCR3 is a microcontroller-class processor core. Overview: https://syntacore.com/products/scr3 This PR introduces two CPUs: * 'syntacore-scr3-rv32' which is rv32imc * 'syntacore-scr3-rv64' which is rv64imac --------- Co-authored-by: Dmitrii Petrov <[email protected]>
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‎clang/test/Driver/riscv-cpus.c

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// RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 -march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s
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// MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64
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// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=syntacore-scr3-rv32 | FileCheck -check-prefix=MCPU-SYNTACORE-SCR3-RV32 %s
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// MCPU-SYNTACORE-SCR3-RV32: "-target-cpu" "syntacore-scr3-rv32"
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// MCPU-SYNTACORE-SCR3-RV32-SAME: "-target-feature" "+m"
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// MCPU-SYNTACORE-SCR3-RV32-SAME: "-target-feature" "+c"
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// MCPU-SYNTACORE-SCR3-RV32-SAME: "-target-feature" "+zicsr"
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// MCPU-SYNTACORE-SCR3-RV32-SAME: "-target-feature" "+zifencei"
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// MCPU-SYNTACORE-SCR3-RV32-SAME: "-target-abi" "ilp32"
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// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr3-rv32 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR3-RV32 %s
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// MTUNE-SYNTACORE-SCR3-RV32: "-tune-cpu" "syntacore-scr3-rv32"
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=syntacore-scr3-rv64 | FileCheck -check-prefix=MCPU-SYNTACORE-SCR3-RV64 %s
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// MCPU-SYNTACORE-SCR3-RV64: "-target-cpu" "syntacore-scr3-rv64"
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// MCPU-SYNTACORE-SCR3-RV64-SAME: "-target-feature" "+m"
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// MCPU-SYNTACORE-SCR3-RV64-SAME: "-target-feature" "+a"
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// MCPU-SYNTACORE-SCR3-RV64-SAME: "-target-feature" "+c"
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// MCPU-SYNTACORE-SCR3-RV64-SAME: "-target-feature" "+zicsr"
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// MCPU-SYNTACORE-SCR3-RV64-SAME: "-target-feature" "+zifencei"
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// MCPU-SYNTACORE-SCR3-RV64-SAME: "-target-abi" "lp64"
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr3-rv64 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR3-RV64 %s
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// MTUNE-SYNTACORE-SCR3-RV64: "-tune-cpu" "syntacore-scr3-rv64"

‎clang/test/Misc/target-invalid-cpu-note.c

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// RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32
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// RISCV32: error: unknown target CPU 'not-a-cpu'
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// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max{{$}}
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// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max, syntacore-scr3-rv32{{$}}
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// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
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// RISCV64: error: unknown target CPU 'not-a-cpu'
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// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, veyron-v1, xiangshan-nanhu{{$}}
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// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, veyron-v1, xiangshan-nanhu{{$}}
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// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
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// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
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// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max, generic, rocket, sifive-7-series{{$}}
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// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max, syntacore-scr3-rv32, generic, rocket, sifive-7-series{{$}}
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// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
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// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
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// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
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// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, syntacore-scr3-rv64, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}

‎llvm/docs/ReleaseNotes.rst

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* Zabha is no longer experimental.
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* B (the collection of the Zba, Zbb, Zbs extensions) is supported.
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* Added smcdeleg, ssccfg, smcsrind, and sscsrind extensions to -march.
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* ``-mcpu=syntacore-scr3-rv32`` and ``-mcpu=syntacore-scr3-rv64`` were added.
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Changes to the WebAssembly Backend
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----------------------------------

‎llvm/lib/Target/RISCV/RISCVProcessors.td

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FeatureStdExtC],
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[TuneNoDefaultUnroll]>;
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def SYNTACORE_SCR3_RV32 : RISCVProcessorModel<"syntacore-scr3-rv32",
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NoSchedModel,
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[Feature32Bit,
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FeatureStdExtI,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtC],
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[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
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def SYNTACORE_SCR3_RV64 : RISCVProcessorModel<"syntacore-scr3-rv64",
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NoSchedModel,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtC],
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[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
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def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
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NoSchedModel,
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[Feature64Bit,

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