@@ -70,7 +70,8 @@ class AMDGPUPostLegalizerCombinerImpl : public Combiner {
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};
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// TODO: Make sure fmin_legacy/fmax_legacy don't canonicalize
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- bool matchFMinFMaxLegacy (MachineInstr &MI, FMinFMaxLegacyInfo &Info) const ;
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+ bool matchFMinFMaxLegacy (MachineInstr &MI, MachineInstr &FCmp,
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+ FMinFMaxLegacyInfo &Info) const ;
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void applySelectFCmpToFMinToFMaxLegacy (MachineInstr &MI,
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const FMinFMaxLegacyInfo &Info) const ;
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@@ -158,17 +159,14 @@ bool AMDGPUPostLegalizerCombinerImpl::tryCombineAll(MachineInstr &MI) const {
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}
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bool AMDGPUPostLegalizerCombinerImpl::matchFMinFMaxLegacy (
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- MachineInstr &MI, FMinFMaxLegacyInfo &Info) const {
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- // FIXME: Type predicate on pattern
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- if (MRI.getType (MI.getOperand (0 ).getReg ()) != LLT::scalar (32 ))
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- return false ;
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-
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- Register Cond = MI.getOperand (1 ).getReg ();
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- if (!MRI.hasOneNonDBGUse (Cond) ||
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- !mi_match (Cond, MRI,
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- m_GFCmp (m_Pred (Info.Pred ), m_Reg (Info.LHS ), m_Reg (Info.RHS ))))
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+ MachineInstr &MI, MachineInstr &FCmp, FMinFMaxLegacyInfo &Info) const {
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+ if (!MRI.hasOneNonDBGUse (FCmp.getOperand (0 ).getReg ()))
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return false ;
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+ Info.Pred =
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+ static_cast <CmpInst::Predicate>(FCmp.getOperand (1 ).getPredicate ());
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+ Info.LHS = FCmp.getOperand (2 ).getReg ();
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+ Info.RHS = FCmp.getOperand (3 ).getReg ();
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Register True = MI.getOperand (2 ).getReg ();
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Register False = MI.getOperand (3 ).getReg ();
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