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Sjoerd Meijer
committed
[AArch64] Default to zero-cycle-zeroing FP registers
It is generally beneficial to prefer "movi d0, #0" over "fmov s0, wzr" as this is most efficient across all cores; it is recognised as a zeroing idiom. For newer cores, fmov instructions can also be eliminated early and there is no difference with movi, but some implementations lack this so is not true for other/older cores. Thus this standardises on using movi as this should always gives the same or better performance than the fmov with wzr. Differential Revision: https://reviews.llvm.org/D99586
1 parent 2935737 commit d5f1131

12 files changed

+73
-65
lines changed

‎llvm/lib/Target/AArch64/AArch64.td

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -147,12 +147,12 @@ def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
147147
def FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true",
148148
"Has zero-cycle zeroing instructions for generic registers">;
149149

150-
def FeatureZCZeroingFP : SubtargetFeature<"zcz-fp", "HasZeroCycleZeroingFP", "true",
151-
"Has zero-cycle zeroing instructions for FP registers">;
150+
def FeatureNoZCZeroingFP : SubtargetFeature<"no-zcz-fp", "HasZeroCycleZeroingFP", "false",
151+
"Has no zero-cycle zeroing instructions for FP registers">;
152152

153153
def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
154154
"Has zero-cycle zeroing instructions",
155-
[FeatureZCZeroingGP, FeatureZCZeroingFP]>;
155+
[FeatureZCZeroingGP]>;
156156

157157
/// ... but the floating-point version doesn't quite work in rare cases on older
158158
/// CPUs.
@@ -915,8 +915,7 @@ def ProcExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3",
915915
FeatureLSLFast,
916916
FeaturePerfMon,
917917
FeaturePostRAScheduler,
918-
FeaturePredictableSelectIsExpensive,
919-
FeatureZCZeroingFP]>;
918+
FeaturePredictableSelectIsExpensive]>;
920919

921920
def ProcExynosM4 : SubtargetFeature<"exynosm4", "ARMProcFamily", "ExynosM3",
922921
"Samsung Exynos-M4 processors",

‎llvm/lib/Target/AArch64/AArch64Subtarget.h

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -196,9 +196,14 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
196196
// HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
197197
bool HasZeroCycleZeroing = false;
198198
bool HasZeroCycleZeroingGP = false;
199-
bool HasZeroCycleZeroingFP = false;
200199
bool HasZeroCycleZeroingFPWorkaround = false;
201200

201+
// It is generally beneficial to rewrite "fmov s0, wzr" to "movi d0, #0".
202+
// as movi is more efficient across all cores. Newer cores can eliminate
203+
// fmovs early and there is no difference with movi, but this not true for
204+
// all implementations.
205+
bool HasZeroCycleZeroingFP = true;
206+
202207
// StrictAlign - Disallow unaligned memory accesses.
203208
bool StrictAlign = false;
204209

‎llvm/test/CodeGen/AArch64/arm64-fast-isel-materialize.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ define float @fmov_float2() {
1515
; CHECK-LABEL: fmov_float2
1616
; CHECK: fmov s0, wzr
1717
; GISEL-LABEL: fmov_float2
18-
; GISEL: fmov s0, wzr
18+
; GISEL: movi d0, #0000000000000000
1919
ret float 0.0e+00
2020
}
2121

@@ -31,7 +31,7 @@ define double @fmov_double2() {
3131
; CHECK-LABEL: fmov_double2
3232
; CHECK: fmov d0, xzr
3333
; GISEL-LABEL: fmov_double2
34-
; GISEL: fmov d0, xzr
34+
; GISEL: movi d0, #0000000000000000
3535
ret double 0.0e+00
3636
}
3737

‎llvm/test/CodeGen/AArch64/arm64-fp-contract-zero.ll

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,16 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
12
; RUN: llc -mtriple=arm64 -fp-contract=fast -o - %s | FileCheck %s
23

34

45
; Make sure we don't try to fold an fneg into +0.0, creating an illegal constant
56
; -0.0. It's also good, though not essential, that we don't resort to a litpool.
67
define double @test_fms_fold(double %a, double %b) {
78
; CHECK-LABEL: test_fms_fold:
8-
; CHECK: fmov {{d[0-9]+}}, xzr
9-
; CHECK: ret
9+
; CHECK: // %bb.0:
10+
; CHECK-NEXT: movi d2, #0000000000000000
11+
; CHECK-NEXT: fmul d1, d1, d2
12+
; CHECK-NEXT: fnmsub d0, d0, d2, d1
13+
; CHECK-NEXT: ret
1014
%mul = fmul double %a, 0.000000e+00
1115
%mul1 = fmul double %b, 0.000000e+00
1216
%sub = fsub double %mul, %mul1

‎llvm/test/CodeGen/AArch64/arm64-rev.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -561,7 +561,7 @@ define void @float_vrev64(float* nocapture %source, <4 x float>* nocapture %dest
561561
;
562562
; FALLBACK-LABEL: float_vrev64:
563563
; FALLBACK: // %bb.0: // %entry
564-
; FALLBACK-NEXT: fmov s0, wzr
564+
; FALLBACK-NEXT: movi d0, #0000000000000000
565565
; FALLBACK-NEXT: mov.s v0[1], v0[0]
566566
; FALLBACK-NEXT: mov.s v0[2], v0[0]
567567
; FALLBACK-NEXT: adrp x8, .LCPI28_0

‎llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,14 @@
1-
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=-zcz | FileCheck %s -check-prefixes=ALL,NONEGP,NONEFP
1+
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=-zcz-gp,+no-zcz-fp | FileCheck %s -check-prefixes=ALL,NONEGP,NONEFP
22
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+zcz | FileCheck %s -check-prefixes=ALL,ZEROGP,ZEROFP
33
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+zcz -mattr=+fullfp16 | FileCheck %s -check-prefixes=ALL,ZEROGP,ZERO16
4-
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+zcz-gp | FileCheck %s -check-prefixes=ALL,ZEROGP,NONEFP
5-
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+zcz-fp | FileCheck %s -check-prefixes=ALL,NONEGP,ZEROFP
4+
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+zcz-gp,+no-zcz-fp | FileCheck %s -check-prefixes=ALL,ZEROGP,NONEFP
5+
; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s -check-prefixes=ALL,NONEGP,ZEROFP
66
; RUN: llc < %s -mtriple=arm64-apple-ios -mcpu=cyclone | FileCheck %s -check-prefixes=ALL,ZEROGP,NONEFP
77
; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=apple-a10 | FileCheck %s -check-prefixes=ALL,ZEROGP,ZEROFP
88
; RUN: llc < %s -mtriple=arm64-apple-ios -mcpu=cyclone -mattr=+fullfp16 | FileCheck %s -check-prefixes=ALL,ZEROGP,NONE16
99
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 | FileCheck %s -check-prefixes=ALL,NONEGP,ZEROFP
1010
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=kryo | FileCheck %s -check-prefixes=ALL,ZEROGP,ZEROFP
11-
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=falkor | FileCheck %s -check-prefixes=ALL,ZEROGP,ZEROFP
11+
; UN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=falkor | FileCheck %s -check-prefixes=ALL,ZEROGP,ZEROFP
1212

1313
declare void @bar(half, float, double, <2 x double>)
1414
declare void @bari(i32, i32)

‎llvm/test/CodeGen/AArch64/f16-imm.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16,CHECK-NOZCZ
2+
; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+fullfp16,+no-zcz-fp | FileCheck %s --check-prefixes=CHECK,CHECK-FP16,CHECK-NOZCZ
33
; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+fullfp16,+zcz | FileCheck %s --check-prefixes=CHECK,CHECK-FP16,CHECK-ZCZ
44
; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=-fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-NOFP16
55

‎llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ define i1 @test_signed_i1_f32(float %f) nounwind {
2020
; CHECK-LABEL: test_signed_i1_f32:
2121
; CHECK: // %bb.0:
2222
; CHECK-NEXT: fmov s1, #-1.00000000
23-
; CHECK-NEXT: fmov s2, wzr
23+
; CHECK-NEXT: movi d2, #0000000000000000
2424
; CHECK-NEXT: fmaxnm s1, s0, s1
2525
; CHECK-NEXT: fminnm s1, s1, s2
2626
; CHECK-NEXT: fcvtzs w8, s1
@@ -243,7 +243,7 @@ define i1 @test_signed_i1_f64(double %f) nounwind {
243243
; CHECK-LABEL: test_signed_i1_f64:
244244
; CHECK: // %bb.0:
245245
; CHECK-NEXT: fmov d1, #-1.00000000
246-
; CHECK-NEXT: fmov d2, xzr
246+
; CHECK-NEXT: movi d2, #0000000000000000
247247
; CHECK-NEXT: fmaxnm d1, d0, d1
248248
; CHECK-NEXT: fminnm d1, d1, d2
249249
; CHECK-NEXT: fcvtzs w8, d1
@@ -462,7 +462,7 @@ define i1 @test_signed_i1_f16(half %f) nounwind {
462462
; CHECK: // %bb.0:
463463
; CHECK-NEXT: fcvt s0, h0
464464
; CHECK-NEXT: fmov s1, #-1.00000000
465-
; CHECK-NEXT: fmov s2, wzr
465+
; CHECK-NEXT: movi d2, #0000000000000000
466466
; CHECK-NEXT: fmaxnm s1, s0, s1
467467
; CHECK-NEXT: fminnm s1, s1, s2
468468
; CHECK-NEXT: fcvtzs w8, s1

‎llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1469,7 +1469,7 @@ define <2 x i1> @test_signed_v2f32_v2i1(<2 x float> %f) {
14691469
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
14701470
; CHECK-NEXT: mov s1, v0.s[1]
14711471
; CHECK-NEXT: fmov s2, #-1.00000000
1472-
; CHECK-NEXT: fmov s3, wzr
1472+
; CHECK-NEXT: movi d3, #0000000000000000
14731473
; CHECK-NEXT: fmaxnm s4, s1, s2
14741474
; CHECK-NEXT: fcmp s1, s1
14751475
; CHECK-NEXT: fmaxnm s1, s0, s2
@@ -1849,7 +1849,7 @@ define <2 x i1> @test_signed_v2f64_v2i1(<2 x double> %f) {
18491849
; CHECK: // %bb.0:
18501850
; CHECK-NEXT: mov d1, v0.d[1]
18511851
; CHECK-NEXT: fmov d2, #-1.00000000
1852-
; CHECK-NEXT: fmov d3, xzr
1852+
; CHECK-NEXT: movi d3, #0000000000000000
18531853
; CHECK-NEXT: fmaxnm d4, d1, d2
18541854
; CHECK-NEXT: fcmp d1, d1
18551855
; CHECK-NEXT: fmaxnm d1, d0, d2
@@ -2212,7 +2212,7 @@ define <4 x i1> @test_signed_v4f16_v4i1(<4 x half> %f) {
22122212
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
22132213
; CHECK-NEXT: fmov s2, #-1.00000000
22142214
; CHECK-NEXT: fcvt s4, h0
2215-
; CHECK-NEXT: fmov s3, wzr
2215+
; CHECK-NEXT: movi d3, #0000000000000000
22162216
; CHECK-NEXT: fmaxnm s5, s4, s2
22172217
; CHECK-NEXT: mov h1, v0.h[1]
22182218
; CHECK-NEXT: fminnm s5, s5, s3

‎llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ declare i128 @llvm.fptoui.sat.i128.f32(float)
1919
define i1 @test_unsigned_i1_f32(float %f) nounwind {
2020
; CHECK-LABEL: test_unsigned_i1_f32:
2121
; CHECK: // %bb.0:
22-
; CHECK-NEXT: fmov s1, wzr
22+
; CHECK-NEXT: movi d1, #0000000000000000
2323
; CHECK-NEXT: fmaxnm s0, s0, s1
2424
; CHECK-NEXT: fmov s1, #1.00000000
2525
; CHECK-NEXT: fminnm s0, s0, s1
@@ -33,7 +33,7 @@ define i1 @test_unsigned_i1_f32(float %f) nounwind {
3333
define i8 @test_unsigned_i8_f32(float %f) nounwind {
3434
; CHECK-LABEL: test_unsigned_i8_f32:
3535
; CHECK: // %bb.0:
36-
; CHECK-NEXT: fmov s1, wzr
36+
; CHECK-NEXT: movi d1, #0000000000000000
3737
; CHECK-NEXT: mov w8, #1132396544
3838
; CHECK-NEXT: fmaxnm s0, s0, s1
3939
; CHECK-NEXT: fmov s1, w8
@@ -48,7 +48,7 @@ define i13 @test_unsigned_i13_f32(float %f) nounwind {
4848
; CHECK-LABEL: test_unsigned_i13_f32:
4949
; CHECK: // %bb.0:
5050
; CHECK-NEXT: mov w8, #63488
51-
; CHECK-NEXT: fmov s1, wzr
51+
; CHECK-NEXT: movi d1, #0000000000000000
5252
; CHECK-NEXT: movk w8, #17919, lsl #16
5353
; CHECK-NEXT: fmaxnm s0, s0, s1
5454
; CHECK-NEXT: fmov s1, w8
@@ -63,7 +63,7 @@ define i16 @test_unsigned_i16_f32(float %f) nounwind {
6363
; CHECK-LABEL: test_unsigned_i16_f32:
6464
; CHECK: // %bb.0:
6565
; CHECK-NEXT: mov w8, #65280
66-
; CHECK-NEXT: fmov s1, wzr
66+
; CHECK-NEXT: movi d1, #0000000000000000
6767
; CHECK-NEXT: movk w8, #18303, lsl #16
6868
; CHECK-NEXT: fmaxnm s0, s0, s1
6969
; CHECK-NEXT: fmov s1, w8
@@ -78,7 +78,7 @@ define i19 @test_unsigned_i19_f32(float %f) nounwind {
7878
; CHECK-LABEL: test_unsigned_i19_f32:
7979
; CHECK: // %bb.0:
8080
; CHECK-NEXT: mov w8, #65504
81-
; CHECK-NEXT: fmov s1, wzr
81+
; CHECK-NEXT: movi d1, #0000000000000000
8282
; CHECK-NEXT: movk w8, #18687, lsl #16
8383
; CHECK-NEXT: fmaxnm s0, s0, s1
8484
; CHECK-NEXT: fmov s1, w8
@@ -198,7 +198,7 @@ declare i128 @llvm.fptoui.sat.i128.f64(double)
198198
define i1 @test_unsigned_i1_f64(double %f) nounwind {
199199
; CHECK-LABEL: test_unsigned_i1_f64:
200200
; CHECK: // %bb.0:
201-
; CHECK-NEXT: fmov d1, xzr
201+
; CHECK-NEXT: movi d1, #0000000000000000
202202
; CHECK-NEXT: fmaxnm d0, d0, d1
203203
; CHECK-NEXT: fmov d1, #1.00000000
204204
; CHECK-NEXT: fminnm d0, d0, d1
@@ -213,7 +213,7 @@ define i8 @test_unsigned_i8_f64(double %f) nounwind {
213213
; CHECK-LABEL: test_unsigned_i8_f64:
214214
; CHECK: // %bb.0:
215215
; CHECK-NEXT: mov x8, #246290604621824
216-
; CHECK-NEXT: fmov d1, xzr
216+
; CHECK-NEXT: movi d1, #0000000000000000
217217
; CHECK-NEXT: movk x8, #16495, lsl #48
218218
; CHECK-NEXT: fmaxnm d0, d0, d1
219219
; CHECK-NEXT: fmov d1, x8
@@ -228,7 +228,7 @@ define i13 @test_unsigned_i13_f64(double %f) nounwind {
228228
; CHECK-LABEL: test_unsigned_i13_f64:
229229
; CHECK: // %bb.0:
230230
; CHECK-NEXT: mov x8, #280375465082880
231-
; CHECK-NEXT: fmov d1, xzr
231+
; CHECK-NEXT: movi d1, #0000000000000000
232232
; CHECK-NEXT: movk x8, #16575, lsl #48
233233
; CHECK-NEXT: fmaxnm d0, d0, d1
234234
; CHECK-NEXT: fmov d1, x8
@@ -243,7 +243,7 @@ define i16 @test_unsigned_i16_f64(double %f) nounwind {
243243
; CHECK-LABEL: test_unsigned_i16_f64:
244244
; CHECK: // %bb.0:
245245
; CHECK-NEXT: mov x8, #281337537757184
246-
; CHECK-NEXT: fmov d1, xzr
246+
; CHECK-NEXT: movi d1, #0000000000000000
247247
; CHECK-NEXT: movk x8, #16623, lsl #48
248248
; CHECK-NEXT: fmaxnm d0, d0, d1
249249
; CHECK-NEXT: fmov d1, x8
@@ -258,7 +258,7 @@ define i19 @test_unsigned_i19_f64(double %f) nounwind {
258258
; CHECK-LABEL: test_unsigned_i19_f64:
259259
; CHECK: // %bb.0:
260260
; CHECK-NEXT: mov x8, #281457796841472
261-
; CHECK-NEXT: fmov d1, xzr
261+
; CHECK-NEXT: movi d1, #0000000000000000
262262
; CHECK-NEXT: movk x8, #16671, lsl #48
263263
; CHECK-NEXT: fmaxnm d0, d0, d1
264264
; CHECK-NEXT: fmov d1, x8
@@ -273,7 +273,7 @@ define i32 @test_unsigned_i32_f64(double %f) nounwind {
273273
; CHECK-LABEL: test_unsigned_i32_f64:
274274
; CHECK: // %bb.0:
275275
; CHECK-NEXT: mov x8, #281474974613504
276-
; CHECK-NEXT: fmov d1, xzr
276+
; CHECK-NEXT: movi d1, #0000000000000000
277277
; CHECK-NEXT: movk x8, #16879, lsl #48
278278
; CHECK-NEXT: fmaxnm d0, d0, d1
279279
; CHECK-NEXT: fmov d1, x8
@@ -288,7 +288,7 @@ define i50 @test_unsigned_i50_f64(double %f) nounwind {
288288
; CHECK-LABEL: test_unsigned_i50_f64:
289289
; CHECK: // %bb.0:
290290
; CHECK-NEXT: mov x8, #-8
291-
; CHECK-NEXT: fmov d1, xzr
291+
; CHECK-NEXT: movi d1, #0000000000000000
292292
; CHECK-NEXT: movk x8, #17167, lsl #48
293293
; CHECK-NEXT: fmaxnm d0, d0, d1
294294
; CHECK-NEXT: fmov d1, x8
@@ -378,7 +378,7 @@ define i1 @test_unsigned_i1_f16(half %f) nounwind {
378378
; CHECK-LABEL: test_unsigned_i1_f16:
379379
; CHECK: // %bb.0:
380380
; CHECK-NEXT: fcvt s0, h0
381-
; CHECK-NEXT: fmov s1, wzr
381+
; CHECK-NEXT: movi d1, #0000000000000000
382382
; CHECK-NEXT: fmaxnm s0, s0, s1
383383
; CHECK-NEXT: fmov s1, #1.00000000
384384
; CHECK-NEXT: fminnm s0, s0, s1
@@ -393,7 +393,7 @@ define i8 @test_unsigned_i8_f16(half %f) nounwind {
393393
; CHECK-LABEL: test_unsigned_i8_f16:
394394
; CHECK: // %bb.0:
395395
; CHECK-NEXT: fcvt s0, h0
396-
; CHECK-NEXT: fmov s1, wzr
396+
; CHECK-NEXT: movi d1, #0000000000000000
397397
; CHECK-NEXT: mov w8, #1132396544
398398
; CHECK-NEXT: fmaxnm s0, s0, s1
399399
; CHECK-NEXT: fmov s1, w8
@@ -409,7 +409,7 @@ define i13 @test_unsigned_i13_f16(half %f) nounwind {
409409
; CHECK: // %bb.0:
410410
; CHECK-NEXT: mov w8, #63488
411411
; CHECK-NEXT: fcvt s0, h0
412-
; CHECK-NEXT: fmov s1, wzr
412+
; CHECK-NEXT: movi d1, #0000000000000000
413413
; CHECK-NEXT: movk w8, #17919, lsl #16
414414
; CHECK-NEXT: fmaxnm s0, s0, s1
415415
; CHECK-NEXT: fmov s1, w8
@@ -425,7 +425,7 @@ define i16 @test_unsigned_i16_f16(half %f) nounwind {
425425
; CHECK: // %bb.0:
426426
; CHECK-NEXT: mov w8, #65280
427427
; CHECK-NEXT: fcvt s0, h0
428-
; CHECK-NEXT: fmov s1, wzr
428+
; CHECK-NEXT: movi d1, #0000000000000000
429429
; CHECK-NEXT: movk w8, #18303, lsl #16
430430
; CHECK-NEXT: fmaxnm s0, s0, s1
431431
; CHECK-NEXT: fmov s1, w8
@@ -441,7 +441,7 @@ define i19 @test_unsigned_i19_f16(half %f) nounwind {
441441
; CHECK: // %bb.0:
442442
; CHECK-NEXT: mov w8, #65504
443443
; CHECK-NEXT: fcvt s0, h0
444-
; CHECK-NEXT: fmov s1, wzr
444+
; CHECK-NEXT: movi d1, #0000000000000000
445445
; CHECK-NEXT: movk w8, #18687, lsl #16
446446
; CHECK-NEXT: fmaxnm s0, s0, s1
447447
; CHECK-NEXT: fmov s1, w8

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