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1 parent cebc837 commit d62c6adCopy full SHA for d62c6ad
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/int-ptr-cast-rv32.mir
@@ -1,5 +1,5 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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-# RUN: llc -march=riscv32 -run-pass=instruction-select -simplify-mir \
+# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir \
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# RUN: -verify-machineinstrs %s -o - | FileCheck %s
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---
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/int-ptr-cast-rv64.mir
-# RUN: llc -march=riscv64 -run-pass=instruction-select -simplify-mir \
+# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir \
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