[GIsel][AArch64] Add missing RegOperand to LeafOperand name changes

Author: jyli0116

llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h

@@ -161,11 +161,11 @@ enum {
   /// - Pred(2) - The predicate to test
   GIM_CheckImmOperandPredicate,
 
-  /// Check a register predicate on the specified instruction.
+  /// Check a leaf predicate on the specified instruction.
   /// - InsnID(ULEB128) - Instruction ID
   /// - OpIdx(ULEB128) - Operand index
   /// - Pred(2) - The predicate to test
-  GIM_CheckRegOperandPredicate,
+  GIM_CheckLeafOperandPredicate,
 
   /// Check a memory operation has the specified atomic ordering.
   /// - InsnID(ULEB128) - Instruction ID

llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h

@@ -410,13 +410,13 @@ bool GIMatchTableExecutor::executeMatchTable(
           return false;
       break;
     }
-    case GIM_CheckRegOperandPredicate: {
+    case GIM_CheckLeafOperandPredicate: {
       uint64_t InsnID = readULEB();
       uint64_t OpIdx = readULEB();
       uint16_t Predicate = readU16();
       DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs()
-                          << CurrentIdx << ": GIM_CheckRegOperandPredicate(MIs["
+                          << CurrentIdx << ": GIM_CheckLeafOperandPredicate(MIs["
                           << InsnID << "]->getOperand(" << OpIdx
                           << "), Predicate=" << Predicate << ")\n");
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");

llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td

@@ -867,10 +867,10 @@ def MULADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3),
 // NOOPT-NEXT:     /*  897 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID),
 // NOOPT-NEXT:     /*  901 */   // MIs[0] src1
 // NOOPT-NEXT:     /*  901 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
-// NOOPT-NEXT:     /*  904 */   GIM_CheckRegOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_leaf),
+// NOOPT-NEXT:     /*  904 */   GIM_CheckLeafOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_leaf),
 // NOOPT-NEXT:     /*  909 */   // MIs[0] src2
 // NOOPT-NEXT:     /*  909 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
-// NOOPT-NEXT:     /*  912 */   GIM_CheckRegOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_leaf),
+// NOOPT-NEXT:     /*  912 */   GIM_CheckLeafOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_MO_Predicate_leaf),
 // NOOPT-NEXT:     /*  917 */   // (sub:{ *:[i32] } GPR32:{ *:[i32] }<<P:Predicate_leaf>>:$src1, GPR32:{ *:[i32] }<<P:Predicate_leaf>>:$src2)  =>  (INSN5:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2)
 // NOOPT-NEXT:     /*  917 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::INSN5),
 // NOOPT-NEXT:     /*  922 */   GIR_RootConstrainSelectedInstOperands,

llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp

@@ -1333,7 +1333,7 @@ void OperandImmPredicateMatcher::emitPredicateOpcodes(MatchTable &Table,
 
 void OperandLeafPredicateMatcher::emitPredicateOpcodes(
     MatchTable &Table, RuleMatcher &Rule) const {
-  Table << MatchTable::Opcode("GIM_CheckRegOperandPredicate")
+  Table << MatchTable::Opcode("GIM_CheckLeafOperandPredicate")
         << MatchTable::Comment("MI") << MatchTable::ULEB128Value(InsnVarID)
         << MatchTable::Comment("MO") << MatchTable::ULEB128Value(OpIdx)
         << MatchTable::Comment("Predicate")