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AMDGPU: Fix si-fix-sgpr-copies asserting on VReg_1 phi (#128903)
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‎llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp

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Original file line numberDiff line numberDiff line change
@@ -669,6 +669,9 @@ bool SIFixSGPRCopies::run(MachineFunction &MF) {
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if (!MO.isReg() || !MO.getReg().isVirtual())
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continue;
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const TargetRegisterClass *SrcRC = MRI->getRegClass(MO.getReg());
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if (SrcRC == &AMDGPU::VReg_1RegClass)
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continue;
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if (TRI->hasVectorRegisters(SrcRC)) {
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const TargetRegisterClass *DestRC =
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TRI->getEquivalentSGPRClass(SrcRC);

‎llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll

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@@ -121,6 +121,68 @@ endloop: ; preds = %if1, %Flow2
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ret void
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}
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define amdgpu_ps void @i1_copy_assert(i1 %v4) {
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; ISA-LABEL: i1_copy_assert:
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; ISA: ; %bb.0: ; %start
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; ISA-NEXT: v_and_b32_e32 v0, 1, v0
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; ISA-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
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; ISA-NEXT: s_mov_b32 s8, 0
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; ISA-NEXT: s_mov_b64 s[0:1], 0
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; ISA-NEXT: ; implicit-def: $sgpr4_sgpr5
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; ISA-NEXT: ; implicit-def: $sgpr2_sgpr3
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; ISA-NEXT: s_branch .LBB1_3
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; ISA-NEXT: .LBB1_1: ; %endif1
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; ISA-NEXT: ; in Loop: Header=BB1_3 Depth=1
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; ISA-NEXT: s_andn2_b64 s[4:5], s[4:5], exec
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; ISA-NEXT: s_and_b64 s[8:9], vcc, exec
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; ISA-NEXT: s_mov_b64 s[6:7], 0
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; ISA-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
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; ISA-NEXT: .LBB1_2: ; %Flow
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; ISA-NEXT: ; in Loop: Header=BB1_3 Depth=1
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; ISA-NEXT: s_and_b64 s[8:9], exec, s[4:5]
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; ISA-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1]
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; ISA-NEXT: s_andn2_b64 s[2:3], s[2:3], exec
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; ISA-NEXT: s_and_b64 s[6:7], s[6:7], exec
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; ISA-NEXT: s_mov_b32 s8, 1
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; ISA-NEXT: s_or_b64 s[2:3], s[2:3], s[6:7]
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; ISA-NEXT: s_andn2_b64 exec, exec, s[0:1]
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; ISA-NEXT: s_cbranch_execz .LBB1_5
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; ISA-NEXT: .LBB1_3: ; %loop
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; ISA-NEXT: ; =>This Inner Loop Header: Depth=1
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; ISA-NEXT: s_or_b64 s[4:5], s[4:5], exec
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; ISA-NEXT: s_cmp_lg_u32 s8, 0
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; ISA-NEXT: s_cbranch_scc1 .LBB1_1
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; ISA-NEXT: ; %bb.4: ; in Loop: Header=BB1_3 Depth=1
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; ISA-NEXT: s_mov_b64 s[6:7], -1
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; ISA-NEXT: s_branch .LBB1_2
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; ISA-NEXT: .LBB1_5: ; %Flow2
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; ISA-NEXT: s_or_b64 exec, exec, s[0:1]
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; ISA-NEXT: v_mov_b32_e32 v0, 0
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; ISA-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[2:3]
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; ISA-NEXT: exp mrt0 off, off, off, off
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; ISA-NEXT: s_endpgm
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start:
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br label %loop
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loop: ; preds = %Flow, %start
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%v1 = phi i32 [ 0, %start ], [ 1, %Flow ]
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%v2 = icmp ugt i32 %v1, 0
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br i1 %v2, label %endif1, label %Flow
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Flow2: ; preds = %Flow
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%spec.select = select i1 %i1, float 1.000000e+00, float 0.000000e+00
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call void @llvm.amdgcn.exp.f32(i32 0, i32 0, float %spec.select, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, i1 false, i1 false)
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ret void
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endif1: ; preds = %loop
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br label %Flow
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Flow: ; preds = %endif1, %loop
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%i = phi i1 [ %v4, %endif1 ], [ true, %loop ]
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%i1 = phi i1 [ false, %endif1 ], [ true, %loop ]
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br i1 %i, label %Flow2, label %loop
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}
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; Function Attrs: nounwind readnone speculatable willreturn
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declare float @llvm.sqrt.f32(float) #0
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‎llvm/test/CodeGen/AMDGPU/i1-divergent-phi-fix-sgpr-copies-assert.mir

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,97 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -run-pass=si-fix-sgpr-copies,si-i1-copies -o - %s | FileCheck %s
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# Make sure SIFixSGPRCopies does not assert on a phi with vreg_1
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# inputs.
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---
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name: i1_copy_assert
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: i1_copy_assert
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 killed [[COPY]], 1, implicit $exec
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; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
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; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
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; CHECK-NEXT: [[DEF1:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.4(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[PHI:%[0-9]+]]:sreg_64 = PHI [[DEF1]], %bb.0, %14, %bb.4
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; CHECK-NEXT: [[PHI1:%[0-9]+]]:sreg_64 = PHI [[DEF]], %bb.0, %8, %bb.4
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; CHECK-NEXT: [[S_MOV_B64_1:%[0-9]+]]:sreg_64 = S_MOV_B64 -1
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY [[S_MOV_B64_1]]
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; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
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; CHECK-NEXT: [[DEF2:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
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; CHECK-NEXT: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[PHI]], $exec, implicit-def $scc
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; CHECK-NEXT: S_CMP_LG_U32 [[DEF2]], killed [[S_MOV_B32_]], implicit-def $scc
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; CHECK-NEXT: S_CBRANCH_SCC1 %bb.3, implicit $scc
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; CHECK-NEXT: S_BRANCH %bb.4
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_64_xexec = COPY %8
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; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
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; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, [[V_MOV_B32_e32_]], [[COPY2]], implicit $exec
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; CHECK-NEXT: S_ENDPGM 0, implicit killed [[V_CNDMASK_B32_e64_]]
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3:
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; CHECK-NEXT: successors: %bb.4(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[S_MOV_B64_2:%[0-9]+]]:sreg_64 = S_MOV_B64 0
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; CHECK-NEXT: [[S_ANDN2_B64_:%[0-9]+]]:sreg_64 = S_ANDN2_B64 [[S_OR_B64_]], $exec, implicit-def $scc
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; CHECK-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[V_CMP_EQ_U32_e64_]], $exec, implicit-def $scc
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; CHECK-NEXT: [[S_OR_B64_1:%[0-9]+]]:sreg_64 = S_OR_B64 [[S_ANDN2_B64_]], [[S_AND_B64_]], implicit-def $scc
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.4:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[PHI2:%[0-9]+]]:sreg_64 = PHI [[S_OR_B64_]], %bb.1, [[S_OR_B64_1]], %bb.3
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; CHECK-NEXT: [[PHI3:%[0-9]+]]:sreg_64 = PHI [[COPY1]], %bb.1, [[S_MOV_B64_2]], %bb.3
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_64 = COPY [[PHI2]]
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; CHECK-NEXT: [[DEF3:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
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; CHECK-NEXT: [[S_ANDN2_B64_1:%[0-9]+]]:sreg_64 = S_ANDN2_B64 [[PHI1]], $exec, implicit-def $scc
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; CHECK-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[PHI3]], $exec, implicit-def $scc
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; CHECK-NEXT: [[S_OR_B64_2:%[0-9]+]]:sreg_64 = S_OR_B64 [[S_ANDN2_B64_1]], [[S_AND_B64_1]], implicit-def $scc
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; CHECK-NEXT: SI_LOOP [[DEF3]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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; CHECK-NEXT: S_BRANCH %bb.2
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bb.0:
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liveins: $vgpr0
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%0:vgpr_32 = COPY $vgpr0
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%1:sreg_64 = V_CMP_EQ_U32_e64 killed %0, 1, implicit $exec
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%2:sreg_64 = S_MOV_B64 0
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%3:vreg_1 = COPY %1
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bb.1:
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%4:sreg_64 = S_MOV_B64 -1
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%5:vreg_1 = COPY %4
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%6:sreg_32 = S_MOV_B32 0
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%7:sreg_32 = IMPLICIT_DEF
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S_CMP_LG_U32 %7, killed %6, implicit-def $scc
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S_CBRANCH_SCC1 %bb.3, implicit $scc
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S_BRANCH %bb.4
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bb.2:
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%8:vreg_1 = PHI %9, %bb.4
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%10:sreg_64_xexec = COPY %8
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%11:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
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%12:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, %11, %10, implicit $exec
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S_ENDPGM 0, implicit killed %12
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bb.3:
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%13:sreg_64 = S_MOV_B64 0
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bb.4:
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%14:vreg_1 = PHI %5, %bb.1, %3, %bb.3
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%9:sreg_64 = PHI %5, %bb.1, %13, %bb.3
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%15:sreg_64 = COPY %14
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%16:sreg_64 = IMPLICIT_DEF
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SI_LOOP %16, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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S_BRANCH %bb.2
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...

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