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Apply reviewer comments to performFNegCombine
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llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Lines changed: 5 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -5213,15 +5213,13 @@ SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N,
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SDValue Cond = N0.getOperand(0);
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SDValue LHS = N0.getOperand(1);
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SDValue RHS = N0.getOperand(2);
5216-
EVT LHVT = LHS.getValueType();
5217-
EVT RHVT = RHS.getValueType();
5218-
// The regression was limited to i32 v2/i32.
5219-
if (RHVT != MVT::i32 && LHVT != MVT::i32)
5216+
EVT VT = LHS.getValueType();
5217+
if (VT != MVT::i32)
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return SDValue();
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5222-
SDValue LFNeg = DAG.getNode(ISD::FNEG, SL, LHVT, LHS);
5223-
SDValue RFNeg = DAG.getNode(ISD::FNEG, SL, RHVT, RHS);
5224-
SDValue Op = DAG.getNode(Opc, SL, LHVT, Cond, LFNeg, RFNeg);
5220+
SDValue LFNeg = DAG.getNode(ISD::FNEG, SL, VT, LHS);
5221+
SDValue RFNeg = DAG.getNode(ISD::FNEG, SL, VT, RHS);
5222+
SDValue Op = DAG.getNode(Opc, SL, VT, Cond, LFNeg, RFNeg);
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return Op;
52265224
}
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case ISD::BITCAST: {

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