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added function that tests if an instruction waits for VA_SDST=0
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llvm/lib/Target/AMDGPU/AMDGPUInsertDelayAlu.cpp

Lines changed: 18 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,9 +14,13 @@
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#include "AMDGPU.h"
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#include "GCNSubtarget.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
17+
#include "SIDefines.h"
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#include "SIInstrInfo.h"
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#include "Utils/AMDGPUBaseInfo.h"
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#include "llvm/ADT/SetVector.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/MC/MCRegister.h"
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#include "llvm/Support/ErrorHandling.h"
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using namespace llvm;
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@@ -57,6 +61,19 @@ class AMDGPUInsertDelayAlu : public MachineFunctionPass {
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return false;
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}
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64+
static bool instructionWaitsForSALUWrites(const MachineInstr &MI) {
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// These instruction types wait for VA_SDST==0 before issuing.
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// S_CBRANCH_EXECZ and S_CBRANCH_VCCZ are covered by SALU flag
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const uint64_t VA_SDST_0 = SIInstrFlags::SALU | SIInstrFlags::EXP |
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SIInstrFlags::DS | SIInstrFlags::SMRD |
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SIInstrFlags::MIMG | SIInstrFlags::VIMAGE |
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SIInstrFlags::VSAMPLE;
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if (MI.getDesc().TSFlags & VA_SDST_0)
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return true;
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return false;
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}
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// Types of delay that can be encoded in an s_delay_alu instruction.
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enum DelayType { VALU, TRANS, SALU, OTHER };
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@@ -365,7 +382,7 @@ class AMDGPUInsertDelayAlu : public MachineFunctionPass {
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DelayType Type = getDelayType(MI.getDesc().TSFlags);
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if (SII->isSALU(MI.getOpcode())) {
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if (instructionWaitsForSALUWrites(MI)) {
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auto It = State.find(lastSGPRfromVALU);
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if (It != State.end()) {
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DelayInfo Info = It->getSecond();

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