Skip to content

Commit d7ac412

Browse files
sdesmalen-armsdesmalen-arm
authored
[AArch64][SME] Fix definition of uclamp/sclamp instructions. (#77619)
For some reason the arguments were in the wrong order.
1 parent af78e5d commit d7ac412

File tree

4 files changed

+17
-25
lines changed

4 files changed

+17
-25
lines changed

‎llvm/lib/Target/AArch64/SMEInstrFormats.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1268,7 +1268,7 @@ multiclass sve2_int_perm_revd<string asm, SDPatternOperator op> {
12681268
}
12691269

12701270
class sve2_clamp<string asm, bits<2> sz, bit U, ZPRRegOp zpr_ty>
1271-
: I<(outs zpr_ty:$Zd), (ins zpr_ty:$Zn, zpr_ty:$Zm, zpr_ty:$_Zd),
1271+
: I<(outs zpr_ty:$Zd), (ins zpr_ty:$_Zd, zpr_ty:$Zn, zpr_ty:$Zm),
12721272
asm, "\t$Zd, $Zn, $Zm", "", []>,
12731273
Sched<[]> {
12741274
bits<5> Zm;

‎llvm/test/CodeGen/AArch64/sve2-min-max-clamp.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33

44
; Replace pattern min(max(v1,v2),v3) by clamp
55

6-
define <vscale x 16 x i8> @uclampi8(<vscale x 16 x i8> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
6+
define <vscale x 16 x i8> @uclampi8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {
77
; CHECK-LABEL: uclampi8:
88
; CHECK: // %bb.0:
99
; CHECK-NEXT: uclamp z0.b, z1.b, z2.b
@@ -13,7 +13,7 @@ define <vscale x 16 x i8> @uclampi8(<vscale x 16 x i8> %c, <vscale x 16 x i8> %a
1313
ret <vscale x 16 x i8> %res
1414
}
1515

16-
define <vscale x 8 x i16> @uclampi16(<vscale x 8 x i16> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
16+
define <vscale x 8 x i16> @uclampi16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {
1717
; CHECK-LABEL: uclampi16:
1818
; CHECK: // %bb.0:
1919
; CHECK-NEXT: uclamp z0.h, z1.h, z2.h
@@ -23,7 +23,7 @@ define <vscale x 8 x i16> @uclampi16(<vscale x 8 x i16> %c, <vscale x 8 x i16> %
2323
ret <vscale x 8 x i16> %res
2424
}
2525

26-
define <vscale x 4 x i32> @uclampi32(<vscale x 4 x i32> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
26+
define <vscale x 4 x i32> @uclampi32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
2727
; CHECK-LABEL: uclampi32:
2828
; CHECK: // %bb.0:
2929
; CHECK-NEXT: uclamp z0.s, z1.s, z2.s
@@ -33,7 +33,7 @@ define <vscale x 4 x i32> @uclampi32(<vscale x 4 x i32> %c, <vscale x 4 x i32> %
3333
ret <vscale x 4 x i32> %res
3434
}
3535

36-
define <vscale x 2 x i64> @uclampi64(<vscale x 2 x i64> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
36+
define <vscale x 2 x i64> @uclampi64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {
3737
; CHECK-LABEL: uclampi64:
3838
; CHECK: // %bb.0:
3939
; CHECK-NEXT: uclamp z0.d, z1.d, z2.d
@@ -43,7 +43,7 @@ define <vscale x 2 x i64> @uclampi64(<vscale x 2 x i64> %c, <vscale x 2 x i64> %
4343
ret <vscale x 2 x i64> %res
4444
}
4545

46-
define <vscale x 16 x i8> @sclampi8(<vscale x 16 x i8> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
46+
define <vscale x 16 x i8> @sclampi8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) {
4747
; CHECK-LABEL: sclampi8:
4848
; CHECK: // %bb.0:
4949
; CHECK-NEXT: sclamp z0.b, z1.b, z2.b
@@ -53,7 +53,7 @@ define <vscale x 16 x i8> @sclampi8(<vscale x 16 x i8> %c, <vscale x 16 x i8> %a
5353
ret <vscale x 16 x i8> %res
5454
}
5555

56-
define <vscale x 8 x i16> @sclampi16(<vscale x 8 x i16> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
56+
define <vscale x 8 x i16> @sclampi16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {
5757
; CHECK-LABEL: sclampi16:
5858
; CHECK: // %bb.0:
5959
; CHECK-NEXT: sclamp z0.h, z1.h, z2.h
@@ -63,7 +63,7 @@ define <vscale x 8 x i16> @sclampi16(<vscale x 8 x i16> %c, <vscale x 8 x i16> %
6363
ret <vscale x 8 x i16> %res
6464
}
6565

66-
define <vscale x 4 x i32> @sclampi32(<vscale x 4 x i32> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
66+
define <vscale x 4 x i32> @sclampi32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
6767
; CHECK-LABEL: sclampi32:
6868
; CHECK: // %bb.0:
6969
; CHECK-NEXT: sclamp z0.s, z1.s, z2.s
@@ -73,7 +73,7 @@ define <vscale x 4 x i32> @sclampi32(<vscale x 4 x i32> %c, <vscale x 4 x i32> %
7373
ret <vscale x 4 x i32> %res
7474
}
7575

76-
define <vscale x 2 x i64> @sclampi64(<vscale x 2 x i64> %c, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
76+
define <vscale x 2 x i64> @sclampi64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {
7777
; CHECK-LABEL: sclampi64:
7878
; CHECK: // %bb.0:
7979
; CHECK-NEXT: sclamp z0.d, z1.d, z2.d

‎llvm/test/CodeGen/AArch64/sve2p1-intrinsics-sclamp.ll

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -6,8 +6,7 @@ target triple = "aarch64-linux-gnu"
66
define <vscale x 16 x i8> @test_sclamp_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) #0 {
77
; CHECK-LABEL: test_sclamp_i8:
88
; CHECK: // %bb.0:
9-
; CHECK-NEXT: sclamp z2.b, z0.b, z1.b
10-
; CHECK-NEXT: mov z0.d, z2.d
9+
; CHECK-NEXT: sclamp z0.b, z1.b, z2.b
1110
; CHECK-NEXT: ret
1211
%res = call <vscale x 16 x i8> @llvm.aarch64.sve.sclamp.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c)
1312
ret <vscale x 16 x i8> %res
@@ -16,8 +15,7 @@ define <vscale x 16 x i8> @test_sclamp_i8(<vscale x 16 x i8> %a, <vscale x 16 x
1615
define <vscale x 8 x i16> @test_sclamp_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) #0 {
1716
; CHECK-LABEL: test_sclamp_i16:
1817
; CHECK: // %bb.0:
19-
; CHECK-NEXT: sclamp z2.h, z0.h, z1.h
20-
; CHECK-NEXT: mov z0.d, z2.d
18+
; CHECK-NEXT: sclamp z0.h, z1.h, z2.h
2119
; CHECK-NEXT: ret
2220
%res = call <vscale x 8 x i16> @llvm.aarch64.sve.sclamp.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c)
2321
ret <vscale x 8 x i16> %res
@@ -26,8 +24,7 @@ define <vscale x 8 x i16> @test_sclamp_i16(<vscale x 8 x i16> %a, <vscale x 8 x
2624
define <vscale x 4 x i32> @test_sclamp_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) #0 {
2725
; CHECK-LABEL: test_sclamp_i32:
2826
; CHECK: // %bb.0:
29-
; CHECK-NEXT: sclamp z2.s, z0.s, z1.s
30-
; CHECK-NEXT: mov z0.d, z2.d
27+
; CHECK-NEXT: sclamp z0.s, z1.s, z2.s
3128
; CHECK-NEXT: ret
3229
%res = call <vscale x 4 x i32> @llvm.aarch64.sve.sclamp.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c)
3330
ret <vscale x 4 x i32> %res
@@ -36,8 +33,7 @@ define <vscale x 4 x i32> @test_sclamp_i32(<vscale x 4 x i32> %a, <vscale x 4 x
3633
define <vscale x 2 x i64> @test_sclamp_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) #0 {
3734
; CHECK-LABEL: test_sclamp_i64:
3835
; CHECK: // %bb.0:
39-
; CHECK-NEXT: sclamp z2.d, z0.d, z1.d
40-
; CHECK-NEXT: mov z0.d, z2.d
36+
; CHECK-NEXT: sclamp z0.d, z1.d, z2.d
4137
; CHECK-NEXT: ret
4238
%res = call <vscale x 2 x i64> @llvm.aarch64.sve.sclamp.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c)
4339
ret <vscale x 2 x i64> %res

‎llvm/test/CodeGen/AArch64/sve2p1-intrinsics-uclamp.ll

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -6,8 +6,7 @@ target triple = "aarch64-linux-gnu"
66
define <vscale x 16 x i8> @test_uclamp_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) #0 {
77
; CHECK-LABEL: test_uclamp_i8:
88
; CHECK: // %bb.0:
9-
; CHECK-NEXT: uclamp z2.b, z0.b, z1.b
10-
; CHECK-NEXT: mov z0.d, z2.d
9+
; CHECK-NEXT: uclamp z0.b, z1.b, z2.b
1110
; CHECK-NEXT: ret
1211
%res = call <vscale x 16 x i8> @llvm.aarch64.sve.uclamp.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c)
1312
ret <vscale x 16 x i8> %res
@@ -16,8 +15,7 @@ define <vscale x 16 x i8> @test_uclamp_i8(<vscale x 16 x i8> %a, <vscale x 16 x
1615
define <vscale x 8 x i16> @test_uclamp_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) #0 {
1716
; CHECK-LABEL: test_uclamp_i16:
1817
; CHECK: // %bb.0:
19-
; CHECK-NEXT: uclamp z2.h, z0.h, z1.h
20-
; CHECK-NEXT: mov z0.d, z2.d
18+
; CHECK-NEXT: uclamp z0.h, z1.h, z2.h
2119
; CHECK-NEXT: ret
2220
%res = call <vscale x 8 x i16> @llvm.aarch64.sve.uclamp.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c)
2321
ret <vscale x 8 x i16> %res
@@ -26,8 +24,7 @@ define <vscale x 8 x i16> @test_uclamp_i16(<vscale x 8 x i16> %a, <vscale x 8 x
2624
define <vscale x 4 x i32> @test_uclamp_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) #0 {
2725
; CHECK-LABEL: test_uclamp_i32:
2826
; CHECK: // %bb.0:
29-
; CHECK-NEXT: uclamp z2.s, z0.s, z1.s
30-
; CHECK-NEXT: mov z0.d, z2.d
27+
; CHECK-NEXT: uclamp z0.s, z1.s, z2.s
3128
; CHECK-NEXT: ret
3229
%res = call <vscale x 4 x i32> @llvm.aarch64.sve.uclamp.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c)
3330
ret <vscale x 4 x i32> %res
@@ -36,8 +33,7 @@ define <vscale x 4 x i32> @test_uclamp_i32(<vscale x 4 x i32> %a, <vscale x 4 x
3633
define <vscale x 2 x i64> @test_uclamp_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) #0 {
3734
; CHECK-LABEL: test_uclamp_i64:
3835
; CHECK: // %bb.0:
39-
; CHECK-NEXT: uclamp z2.d, z0.d, z1.d
40-
; CHECK-NEXT: mov z0.d, z2.d
36+
; CHECK-NEXT: uclamp z0.d, z1.d, z2.d
4137
; CHECK-NEXT: ret
4238
%res = call <vscale x 2 x i64> @llvm.aarch64.sve.uclamp.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c)
4339
ret <vscale x 2 x i64> %res

0 commit comments

Comments
 (0)