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| 1 | +// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.3-library -emit-llvm -disable-llvm-passes -o - %s | FileCheck %s --enable-var-scope |
| 2 | + |
| 3 | +// CHECK-LABEL: define void {{.*}}arr_assign1 |
| 4 | +// CHECK: [[Arr:%.*]] = alloca [2 x i32], align 4 |
| 5 | +// CHECK-NEXT: [[Arr2:%.*]] = alloca [2 x i32], align 4 |
| 6 | +// CHECK-NOT: alloca |
| 7 | +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[Arr]], ptr align 4 {{@.*}}, i32 8, i1 false) |
| 8 | +// CHECK-NEXT: call void @llvm.memset.p0.i32(ptr align 4 [[Arr2]], i8 0, i32 8, i1 false) |
| 9 | +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[Arr]], ptr align 4 [[Arr2]], i32 8, i1 false) |
| 10 | +// CHECK-NEXT: ret void |
| 11 | +void arr_assign1() { |
| 12 | + int Arr[2] = {0, 1}; |
| 13 | + int Arr2[2] = {0, 0}; |
| 14 | + Arr = Arr2; |
| 15 | +} |
| 16 | + |
| 17 | +// CHECK-LABEL: define void {{.*}}arr_assign2 |
| 18 | +// CHECK: [[Arr:%.*]] = alloca [2 x i32], align 4 |
| 19 | +// CHECK-NEXT: [[Arr2:%.*]] = alloca [2 x i32], align 4 |
| 20 | +// CHECK-NEXT: [[Arr3:%.*]] = alloca [2 x i32], align 4 |
| 21 | +// CHECK-NOT: alloca |
| 22 | +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[Arr]], ptr align 4 {{@.*}}, i32 8, i1 false) |
| 23 | +// CHECK-NEXT: call void @llvm.memset.p0.i32(ptr align 4 [[Arr2]], i8 0, i32 8, i1 false) |
| 24 | +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[Arr3]], ptr align 4 {{@.*}}, i32 8, i1 false) |
| 25 | +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[Arr2]], ptr align 4 [[Arr3]], i32 8, i1 false) |
| 26 | +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[Arr]], ptr align 4 [[Arr2]], i32 8, i1 false) |
| 27 | +// CHECK-NEXT: ret void |
| 28 | +void arr_assign2() { |
| 29 | + int Arr[2] = {0, 1}; |
| 30 | + int Arr2[2] = {0, 0}; |
| 31 | + int Arr3[2] = {3, 4}; |
| 32 | + Arr = Arr2 = Arr3; |
| 33 | +} |
| 34 | + |
| 35 | +// CHECK-LABEL: define void {{.*}}arr_assign3 |
| 36 | +// CHECK: [[Arr3:%.*]] = alloca [2 x [2 x i32]], align 4 |
| 37 | +// CHECK-NEXT: [[Arr4:%.*]] = alloca [2 x [2 x i32]], align 4 |
| 38 | +// CHECK-NOT: alloca |
| 39 | +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[Arr3]], ptr align 4 {{@.*}}, i32 16, i1 false) |
| 40 | +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[Arr4]], ptr align 4 {{@.*}}, i32 16, i1 false) |
| 41 | +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[Arr3]], ptr align 4 [[Arr4]], i32 16, i1 false) |
| 42 | +// CHECK-NEXT: ret void |
| 43 | +void arr_assign3() { |
| 44 | + int Arr2[2][2] = {{0, 0}, {1, 1}}; |
| 45 | + int Arr3[2][2] = {{1, 1}, {0, 0}}; |
| 46 | + Arr2 = Arr3; |
| 47 | +} |
| 48 | + |
| 49 | +// CHECK-LABEL: define void {{.*}}arr_assign4 |
| 50 | +// CHECK: [[Arr:%.*]] = alloca [2 x i32], align 4 |
| 51 | +// CHECK-NEXT: [[Arr2:%.*]] = alloca [2 x i32], align 4 |
| 52 | +// CHECK-NOT: alloca |
| 53 | +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[Arr]], ptr align 4 {{@.*}}, i32 8, i1 false) |
| 54 | +// CHECK-NEXT: call void @llvm.memset.p0.i32(ptr align 4 [[Arr2]], i8 0, i32 8, i1 false) |
| 55 | +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[Arr]], ptr align 4 [[Arr2]], i32 8, i1 false) |
| 56 | +// CHECK-NEXT: [[Idx:%.*]] = getelementptr inbounds [2 x i32], ptr [[Arr]], i32 0, i32 0 |
| 57 | +// CHECK-NEXT: store i32 6, ptr [[Idx]], align 4 |
| 58 | +// CHECK-NEXT: ret void |
| 59 | +void arr_assign4() { |
| 60 | + int Arr[2] = {0, 1}; |
| 61 | + int Arr2[2] = {0, 0}; |
| 62 | + (Arr = Arr2)[0] = 6; |
| 63 | +} |
| 64 | + |
| 65 | +// CHECK-LABEL: define void {{.*}}arr_assign5 |
| 66 | +// CHECK: [[Arr:%.*]] = alloca [2 x i32], align 4 |
| 67 | +// CHECK-NEXT: [[Arr2:%.*]] = alloca [2 x i32], align 4 |
| 68 | +// CHECK-NEXT: [[Arr3:%.*]] = alloca [2 x i32], align 4 |
| 69 | +// CHECK-NOT: alloca |
| 70 | +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[Arr]], ptr align 4 {{@.*}}, i32 8, i1 false) |
| 71 | +// CHECK-NEXT: call void @llvm.memset.p0.i32(ptr align 4 [[Arr2]], i8 0, i32 8, i1 false) |
| 72 | +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[Arr3]], ptr align 4 {{@.*}}, i32 8, i1 false) |
| 73 | +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[Arr2]], ptr align 4 [[Arr3]], i32 8, i1 false) |
| 74 | +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[Arr]], ptr align 4 [[Arr2]], i32 8, i1 false) |
| 75 | +// CHECK-NEXT: [[Idx:%.*]] = getelementptr inbounds [2 x i32], ptr [[Arr]], i32 0, i32 0 |
| 76 | +// CHECK-NEXT: store i32 6, ptr [[Idx]], align 4 |
| 77 | +// CHECK-NEXT: ret void |
| 78 | +void arr_assign5() { |
| 79 | + int Arr[2] = {0, 1}; |
| 80 | + int Arr2[2] = {0, 0}; |
| 81 | + int Arr3[2] = {3, 4}; |
| 82 | + (Arr = Arr2 = Arr3)[0] = 6; |
| 83 | +} |
| 84 | + |
| 85 | +// CHECK-LABEL: define void {{.*}}arr_assign6 |
| 86 | +// CHECK: [[Arr3:%.*]] = alloca [2 x [2 x i32]], align 4 |
| 87 | +// CHECK-NEXT: [[Arr4:%.*]] = alloca [2 x [2 x i32]], align 4 |
| 88 | +// CHECK-NOT: alloca |
| 89 | +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[Arr3]], ptr align 4 {{@.*}}, i32 16, i1 false) |
| 90 | +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[Arr4]], ptr align 4 {{@.*}}, i32 16, i1 false) |
| 91 | +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[Arr3]], ptr align 4 [[Arr4]], i32 16, i1 false) |
| 92 | +// CHECK-NEXT: [[Idx:%.*]] = getelementptr inbounds [2 x [2 x i32]], ptr [[Arr3]], i32 0, i32 0 |
| 93 | +// CHECK-NEXT: [[Idx2:%.*]] = getelementptr inbounds [2 x i32], ptr [[Idx]], i32 0, i32 0 |
| 94 | +// CHECK-NEXT: store i32 6, ptr [[Idx2]], align 4 |
| 95 | +// CHECK-NEXT: ret void |
| 96 | +void arr_assign6() { |
| 97 | + int Arr[2][2] = {{0, 0}, {1, 1}}; |
| 98 | + int Arr2[2][2] = {{1, 1}, {0, 0}}; |
| 99 | + (Arr = Arr2)[0][0] = 6; |
| 100 | +} |
| 101 | + |
| 102 | +// CHECK-LABEL: define void {{.*}}arr_assign7 |
| 103 | +// CHECK: [[Arr3:%.*]] = alloca [2 x [2 x i32]], align 4 |
| 104 | +// CHECK-NEXT: [[Arr4:%.*]] = alloca [2 x [2 x i32]], align 4 |
| 105 | +// CHECK-NEXT: [[Tmp:%.*]] = alloca [2 x i32], align 4 |
| 106 | +// CHECK-NOT: alloca |
| 107 | +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[Arr3]], ptr align 4 {{@.*}}, i32 16, i1 false) |
| 108 | +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[Arr4]], ptr align 4 {{@.*}}, i32 16, i1 false) |
| 109 | +// CHECK-NEXT: store i32 6, ptr [[Tmp]], align 4 |
| 110 | +// CHECK-NEXT: [[AIE:%.*]] = getelementptr inbounds i32, ptr [[Tmp]], i32 1 |
| 111 | +// CHECK-NEXT: store i32 6, ptr [[AIE]], align 4 |
| 112 | +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[Arr3]], ptr align 4 [[Arr4]], i32 16, i1 false) |
| 113 | +// CHECK-NEXT: [[Idx:%.*]] = getelementptr inbounds [2 x [2 x i32]], ptr [[Arr3]], i32 0, i32 0 |
| 114 | +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[Idx]], ptr align 4 [[Tmp]], i32 8, i1 false) |
| 115 | +// CHECK-NEXT: ret void |
| 116 | +void arr_assign7() { |
| 117 | + int Arr[2][2] = {{0, 1}, {2, 3}}; |
| 118 | + int Arr2[2][2] = {{0, 0}, {1, 1}}; |
| 119 | + (Arr = Arr2)[0] = {6, 6}; |
| 120 | +} |
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