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KanRobertKanRobert
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[X86][MC] Keep backward compatibility in inline asm for constraints (#73529)
Not use r16-r31 with 'q','r','l' constraint for backward compatibility
1 parent 1ece4d3 commit d9221da

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5 files changed

+49
-26
lines changed

5 files changed

+49
-26
lines changed

‎llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -56939,13 +56939,13 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
5693956939
case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
5694056940
if (Subtarget.is64Bit()) {
5694156941
if (VT == MVT::i8 || VT == MVT::i1)
56942-
return std::make_pair(0U, &X86::GR8RegClass);
56942+
return std::make_pair(0U, &X86::GR8_NOREX2RegClass);
5694356943
if (VT == MVT::i16)
56944-
return std::make_pair(0U, &X86::GR16RegClass);
56944+
return std::make_pair(0U, &X86::GR16_NOREX2RegClass);
5694556945
if (VT == MVT::i32 || VT == MVT::f32)
56946-
return std::make_pair(0U, &X86::GR32RegClass);
56946+
return std::make_pair(0U, &X86::GR32_NOREX2RegClass);
5694756947
if (VT != MVT::f80 && !VT.isVector())
56948-
return std::make_pair(0U, &X86::GR64RegClass);
56948+
return std::make_pair(0U, &X86::GR64_NOREX2RegClass);
5694956949
break;
5695056950
}
5695156951
[[fallthrough]];
@@ -56964,14 +56964,14 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
5696456964
case 'r': // GENERAL_REGS
5696556965
case 'l': // INDEX_REGS
5696656966
if (VT == MVT::i8 || VT == MVT::i1)
56967-
return std::make_pair(0U, &X86::GR8RegClass);
56967+
return std::make_pair(0U, &X86::GR8_NOREX2RegClass);
5696856968
if (VT == MVT::i16)
56969-
return std::make_pair(0U, &X86::GR16RegClass);
56969+
return std::make_pair(0U, &X86::GR16_NOREX2RegClass);
5697056970
if (VT == MVT::i32 || VT == MVT::f32 ||
5697156971
(!VT.isVector() && !Subtarget.is64Bit()))
56972-
return std::make_pair(0U, &X86::GR32RegClass);
56972+
return std::make_pair(0U, &X86::GR32_NOREX2RegClass);
5697356973
if (VT != MVT::f80 && !VT.isVector())
56974-
return std::make_pair(0U, &X86::GR64RegClass);
56974+
return std::make_pair(0U, &X86::GR64_NOREX2RegClass);
5697556975
break;
5697656976
case 'R': // LEGACY_REGS
5697756977
if (VT == MVT::i8 || VT == MVT::i1)

‎llvm/test/CodeGen/X86/apx/asm-constraint.ll

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
; Check r16-r31 can not be used with 'q','r','l' constraint for backward compatibility.
2+
; RUN: not llc < %s -mtriple=x86_64-unknown-unknown -mattr=+egpr 2>&1 | FileCheck %s
3+
4+
define void @q() {
5+
; CHECK: error: inline assembly requires more registers than available
6+
%a = call i32 asm sideeffect "movq %rax, $0", "=q,~{rax},~{rbx},~{rcx},~{rdx},~{rdi},~{rsi},~{rbp},~{rsp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
7+
ret void
8+
}
9+
10+
define void @r() {
11+
; CHECK: error: inline assembly requires more registers than available
12+
%a = call i32 asm sideeffect "movq %rax, $0", "=r,~{rax},~{rbx},~{rcx},~{rdx},~{rdi},~{rsi},~{rbp},~{rsp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
13+
ret void
14+
}
15+
16+
define void @l() {
17+
; CHECK: error: inline assembly requires more registers than available
18+
%a = call i32 asm sideeffect "movq %rax, $0", "=l,~{rax},~{rbx},~{rcx},~{rdx},~{rdi},~{rsi},~{rbp},~{rsp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
19+
ret void
20+
}
21+

‎llvm/test/CodeGen/X86/callbr-asm-bb-exports.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616
; CHECK-NEXT: t2: i32,ch = CopyFromReg t0, Register:i32 %2
1717
; CHECK-NEXT: t8: i32 = add t2, Constant:i32<4>
1818
; CHECK-NEXT: t22: ch,glue = CopyToReg t17, Register:i32 %5, t8
19-
; CHECK-NEXT: t29: ch,glue = inlineasm_br t22, TargetExternalSymbol:i64'xorl $0, $0; jmp ${1:l}', MDNode:ch<null>, TargetConstant:i64<0>, TargetConstant:i32<2359305>, Register:i32 %5, TargetConstant:i64<13>, BasicBlock:ch<fail 0x{{[0-9a-f]+}}>, TargetConstant:i32<12>, Register:i32 $df, TargetConstant:i32<12>, Register:i16 $fpsw, TargetConstant:i32<12>, Register:i32 $eflags, t22:1
19+
; CHECK-NEXT: t29: ch,glue = inlineasm_br t22, TargetExternalSymbol:i64'xorl $0, $0; jmp ${1:l}', MDNode:ch<null>, TargetConstant:i64<0>, TargetConstant:i32<2686985>, Register:i32 %5, TargetConstant:i64<13>, BasicBlock:ch<fail 0x{{[0-9a-f]+}}>, TargetConstant:i32<12>, Register:i32 $df, TargetConstant:i32<12>, Register:i16 $fpsw, TargetConstant:i32<12>, Register:i32 $eflags, t22:1
2020

2121
define i32 @test(i32 %a, i32 %b, i32 %c) {
2222
entry:

‎llvm/test/CodeGen/X86/callbr-asm-outputs-indirect-isel-m32.ll

Lines changed: 11 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -10,11 +10,12 @@ define i8 @emulator_cmpxchg_emulated() {
1010
; CHECK-NEXT: successors: %bb.1(0x80000000), %bb.2(0x00000000)
1111
; CHECK-NEXT: {{ $}}
1212
; CHECK-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm $noreg, 1, $noreg, 0, $noreg :: (load (s32) from `ptr null`, align 8)
13-
; CHECK-NEXT: INLINEASM_BR &"", 16 /* maystore attdialect */, 2359306 /* regdef:GR32 */, def %2, 2359306 /* regdef:GR32 */, def %3, 2147549193 /* reguse tiedto:$1 */, [[MOV32rm]](tied-def 5), 13 /* imm */, %bb.2
14-
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $eflags
15-
; CHECK-NEXT: $eflags = COPY [[COPY]]
13+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32_norex2 = COPY [[MOV32rm]]
14+
; CHECK-NEXT: INLINEASM_BR &"", 16 /* maystore attdialect */, 2359306 /* regdef:GR32 */, def %2, 2686986 /* regdef:GR32_NOREX2 */, def %3, 2147549193 /* reguse tiedto:$1 */, [[COPY]](tied-def 5), 13 /* imm */, %bb.2
15+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $eflags
16+
; CHECK-NEXT: $eflags = COPY [[COPY1]]
1617
; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
17-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY %3
18+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY %3
1819
; CHECK-NEXT: JMP_1 %bb.1
1920
; CHECK-NEXT: {{ $}}
2021
; CHECK-NEXT: bb.1.asm.fallthrough:
@@ -49,15 +50,16 @@ define i32 @emulator_cmpxchg_emulated2() {
4950
; CHECK-NEXT: successors: %bb.1(0x80000000), %bb.2(0x00000000)
5051
; CHECK-NEXT: {{ $}}
5152
; CHECK-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm $noreg, 1, $noreg, 0, $noreg :: (load (s32) from `ptr null`, align 8)
52-
; CHECK-NEXT: INLINEASM_BR &"", 16 /* maystore attdialect */, 2359306 /* regdef:GR32 */, def %2, 2359306 /* regdef:GR32 */, def %3, 2147549193 /* reguse tiedto:$1 */, [[MOV32rm]](tied-def 5), 13 /* imm */, %bb.2
53-
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $eflags
54-
; CHECK-NEXT: $eflags = COPY [[COPY]]
53+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32_norex2 = COPY [[MOV32rm]]
54+
; CHECK-NEXT: INLINEASM_BR &"", 16 /* maystore attdialect */, 2359306 /* regdef:GR32 */, def %2, 2686986 /* regdef:GR32_NOREX2 */, def %3, 2147549193 /* reguse tiedto:$1 */, [[COPY]](tied-def 5), 13 /* imm */, %bb.2
55+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $eflags
56+
; CHECK-NEXT: $eflags = COPY [[COPY1]]
5557
; CHECK-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
56-
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY %3
58+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY %3
5759
; CHECK-NEXT: JMP_1 %bb.1
5860
; CHECK-NEXT: {{ $}}
5961
; CHECK-NEXT: bb.1.asm.fallthrough:
60-
; CHECK-NEXT: $eax = COPY [[COPY1]]
62+
; CHECK-NEXT: $eax = COPY [[COPY2]]
6163
; CHECK-NEXT: RET 0, $eax
6264
; CHECK-NEXT: {{ $}}
6365
; CHECK-NEXT: bb.2.efaultu64.split (machine-block-address-taken, inlineasm-br-indirect-target):

‎llvm/test/CodeGen/X86/callbr-asm-outputs-indirect-isel.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ define i32 @test0() {
1010
; CHECK: bb.0 (%ir-block.0):
1111
; CHECK-NEXT: successors: %bb.1(0x80000000), %bb.2(0x00000000)
1212
; CHECK-NEXT: {{ $}}
13-
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 2359306 /* regdef:GR32 */, def %1, 13 /* imm */, %bb.2
13+
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 2686986 /* regdef:GR32_NOREX2 */, def %1, 13 /* imm */, %bb.2
1414
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY %1
1515
; CHECK-NEXT: JMP_1 %bb.1
1616
; CHECK-NEXT: {{ $}}
@@ -39,7 +39,7 @@ define i32 @test1() {
3939
; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.1(0x00000000)
4040
; CHECK-NEXT: {{ $}}
4141
; CHECK-NEXT: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 42
42-
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 2359306 /* regdef:GR32 */, def %4, 13 /* imm */, %bb.1
42+
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 2686986 /* regdef:GR32_NOREX2 */, def %4, 13 /* imm */, %bb.1
4343
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY %4
4444
; CHECK-NEXT: JMP_1 %bb.2
4545
; CHECK-NEXT: {{ $}}
@@ -72,7 +72,7 @@ define i32 @test2() {
7272
; CHECK-NEXT: successors: %bb.2(0x80000000), %bb.1(0x00000000)
7373
; CHECK-NEXT: {{ $}}
7474
; CHECK-NEXT: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 42
75-
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 2359306 /* regdef:GR32 */, def %5, 2359306 /* regdef:GR32 */, def %6, 13 /* imm */, %bb.1
75+
; CHECK-NEXT: INLINEASM_BR &"", 0 /* attdialect */, 2686986 /* regdef:GR32_NOREX2 */, def %5, 2686986 /* regdef:GR32_NOREX2 */, def %6, 13 /* imm */, %bb.1
7676
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY %6
7777
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY %5
7878
; CHECK-NEXT: JMP_1 %bb.2
@@ -232,15 +232,15 @@ define i64 @test6() {
232232
; CHECK-NEXT: liveins: $rdx
233233
; CHECK-NEXT: {{ $}}
234234
; CHECK-NEXT: [[COPY4:%[0-9]+]]:gr64 = COPY $rdx
235-
; CHECK-NEXT: %3:gr64 = COPY [[COPY4]]
235+
; CHECK-NEXT: [[COPY5:%[0-9]+]]:gr64 = COPY [[COPY4]]
236236
; CHECK-NEXT: JMP_1 %bb.2
237237
; CHECK-NEXT: {{ $}}
238238
; CHECK-NEXT: bb.4.foo.split2 (machine-block-address-taken, inlineasm-br-indirect-target):
239239
; CHECK-NEXT: successors: %bb.2(0x80000000)
240240
; CHECK-NEXT: liveins: $rbx
241241
; CHECK-NEXT: {{ $}}
242242
; CHECK-NEXT: [[COPY6:%[0-9]+]]:gr64 = COPY $rbx
243-
; CHECK-NEXT: %4:gr64 = COPY [[COPY6]]
243+
; CHECK-NEXT: [[COPY7:%[0-9]+]]:gr64 = COPY [[COPY6]]
244244
; CHECK-NEXT: JMP_1 %bb.2
245245
entry:
246246
%0 = callbr i64 asm "", "={dx},!i"()
@@ -291,7 +291,7 @@ define i32 @test7() {
291291
; CHECK-NEXT: liveins: $edx
292292
; CHECK-NEXT: {{ $}}
293293
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr32 = COPY $edx
294-
; CHECK-NEXT: %2:gr32 = COPY [[COPY3]]
294+
; CHECK-NEXT: [[COPY4:%[0-9]+]]:gr32 = COPY [[COPY3]]
295295
; CHECK-NEXT: JMP_1 %bb.1
296296
entry:
297297
br label %retry
@@ -317,8 +317,8 @@ define i32 @test8() {
317317
; CHECK: bb.0.entry:
318318
; CHECK-NEXT: successors: %bb.1(0x80000000)
319319
; CHECK-NEXT: {{ $}}
320-
; CHECK-NEXT: INLINEASM_BR &"# $0", 0 /* attdialect */, 2359306 /* regdef:GR32 */, def %1, 13 /* imm */, %bb.1
321-
; CHECK-NEXT: %0:gr32 = COPY %1
320+
; CHECK-NEXT: INLINEASM_BR &"# $0", 0 /* attdialect */, 2686986 /* regdef:GR32_NOREX2 */, def %1, 13 /* imm */, %bb.1
321+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY %1
322322
; CHECK-NEXT: JMP_1 %bb.1
323323
; CHECK-NEXT: {{ $}}
324324
; CHECK-NEXT: bb.1.cleanup (machine-block-address-taken, inlineasm-br-indirect-target):

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