[RISCV] Merge vmerge into its ops if both masks are the same

We currently only allow a vmerge to be merged into its ops if the op isn't
masked or if the vmerge has an all ones mask. We can extend this to also allow
cases where they share the same mask.

Author: lukel97

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

@@ -3570,12 +3570,27 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
     // The vmerge instruction must be TU.
     if (isImplicitDef(Merge))
       return false;
-    // The vmerge instruction must have an all 1s mask since we're going to keep
-    // the mask from the True instruction.
-    // FIXME: Support mask agnostic True instruction which would have an
-    // undef merge operand.
-    if (Mask && !usesAllOnesMask(Mask, Glue))
-      return false;
+    if (Mask) {
+      // THE vmerge instruction must have an all 1s mask or equal to True's mask
+      // since we're going to keep the mask from the True instruction.
+      // FIXME: Support mask agnostic True instruction which would have an
+      // undef merge operand.
+      assert(Glue.getNode() == N->getGluedNode());
+      // We're expecting something like:
+      // t24: nxv2i32 = PseudoVMERGE_VVM_M1 ..., $v0, ..., t27:1
+      //   t23: nxv2i32 = PseudoVADD_VV_M1_MASK ..., $v0, ..., t29:1
+      //     t29: ch,glue = CopyToReg t0, $v0, t8
+      //   t27: ch,glue = CopyToReg t0, $v0, t8
+      assert(Glue->getOpcode() == ISD::CopyToReg);
+      assert(True->getGluedNode()->getOpcode() == ISD::CopyToReg);
+      assert(Glue->getOperand(1) == Mask);
+      assert(True->getGluedNode()->getOperand(1) ==
+             True->getOperand(Info->MaskOpIdx));
+      SDValue TrueMask = N->getGluedNode()->getOperand(2);
+      SDValue NMask = True->getGluedNode()->getOperand(2);
+      if (!usesAllOnesMask(Mask, Glue) && TrueMask != NMask)
+        return false;
+    }
   }
 
   // Skip if True has side effect.

llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll

@@ -22,10 +22,8 @@ declare <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32(<vscale x 2 x i
 define <vscale x 2 x i32> @vmerge_vadd_same_mask(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, <vscale x 2 x i1> %m, i64 %vl) {
 ; CHECK-LABEL: vmerge_vadd_same_mask:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT:    vadd.vv v9, v9, v10, v0.t
-; CHECK-NEXT:    vsetvli zero, zero, e32, m1, tu, ma
-; CHECK-NEXT:    vmerge.vvm v8, v8, v9, v0
+; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, mu
+; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t
 ; CHECK-NEXT:    ret
   %a = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> poison, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, <vscale x 2 x i1> %m, i64 %vl, i64 0)
   %b = call <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.nxv2i32(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %passthru, <vscale x 2 x i32> %a, <vscale x 2 x i1> %m, i64 %vl)
@@ -278,10 +276,8 @@ declare <vscale x 2 x i32>  @llvm.vp.add.nxv2i32(<vscale x 2 x i32>, <vscale x 2
 define <vscale x 2 x i32> @vmerge_vadd(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, <vscale x 2 x i1> %m, i32 zeroext %evl) {
 ; CHECK-LABEL: vmerge_vadd:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT:    vadd.vv v9, v9, v10, v0.t
-; CHECK-NEXT:    vsetvli zero, zero, e32, m1, tu, ma
-; CHECK-NEXT:    vmerge.vvm v8, v8, v9, v0
+; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, mu
+; CHECK-NEXT:    vadd.vv v8, v9, v10, v0.t
 ; CHECK-NEXT:    ret
   %1 = call <vscale x 2 x i32> @llvm.vp.add.nxv2i32(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y, <vscale x 2 x i1> %m, i32 %evl)
   %2 = call <vscale x 2 x i32> @llvm.vp.merge.nxv2i32(<vscale x 2 x i1> %m, <vscale x 2 x i32> %1, <vscale x 2 x i32> %passthru, i32 %evl)

llvm/test/CodeGen/RISCV/rvv/vfwmacc-vp.ll

@@ -89,11 +89,8 @@ define <vscale x 1 x float> @vfmacc_vv_nxv1f32_tu(<vscale x 1 x half> %a, <vscal
 define <vscale x 1 x float> @vfmacc_vv_nxv1f32_masked__tu(<vscale x 1 x half> %a, <vscale x 1 x half> %b, <vscale x 1 x float> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {
 ; ZVFH-LABEL: vfmacc_vv_nxv1f32_masked__tu:
 ; ZVFH:       # %bb.0:
-; ZVFH-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
-; ZVFH-NEXT:    vmv1r.v v11, v10
-; ZVFH-NEXT:    vfwmacc.vv v11, v8, v9, v0.t
-; ZVFH-NEXT:    vsetvli zero, zero, e32, mf2, tu, ma
-; ZVFH-NEXT:    vmerge.vvm v10, v10, v11, v0
+; ZVFH-NEXT:    vsetvli zero, a0, e16, mf4, tu, mu
+; ZVFH-NEXT:    vfwmacc.vv v10, v8, v9, v0.t
 ; ZVFH-NEXT:    vmv1r.v v8, v10
 ; ZVFH-NEXT:    ret
 ;