Skip to content

Commit d999ae6

Browse files
author
Thorsten Schütt
authored
Revert "[GlobalISel] Combine [s,z]ext of undef into 0 (#117439)"
This reverts commit 4516263.
1 parent abc2703 commit d999ae6

File tree

5 files changed

+23
-84
lines changed

5 files changed

+23
-84
lines changed

‎llvm/include/llvm/Target/GlobalISel/Combine.td

Lines changed: 2 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -428,7 +428,7 @@ def unary_undef_to_zero: GICombineRule<
428428
// replaced with undef.
429429
def propagate_undef_any_op: GICombineRule<
430430
(defs root:$root),
431-
(match (wip_match_opcode G_ADD, G_FPTOSI, G_FPTOUI, G_SUB, G_XOR, G_TRUNC, G_BITCAST):$root,
431+
(match (wip_match_opcode G_ADD, G_FPTOSI, G_FPTOUI, G_SUB, G_XOR, G_TRUNC, G_BITCAST, G_ANYEXT):$root,
432432
[{ return Helper.matchAnyExplicitUseIsUndef(*${root}); }]),
433433
(apply [{ Helper.replaceInstWithUndef(*${root}); }])>;
434434

@@ -1857,26 +1857,6 @@ class integer_of_opcode<Instruction castOpcode> : GICombineRule <
18571857

18581858
def integer_of_truncate : integer_of_opcode<G_TRUNC>;
18591859

1860-
def anyext_undef: GICombineRule<
1861-
(defs root:$root),
1862-
(match (G_IMPLICIT_DEF $undef),
1863-
(G_ANYEXT $root, $undef):$Aext),
1864-
(apply [{ Helper.replaceInstWithUndef(*${Aext}); }])>;
1865-
1866-
def zext_undef: GICombineRule<
1867-
(defs root:$root),
1868-
(match (G_IMPLICIT_DEF $undef),
1869-
(G_ZEXT $root, $undef):$Zext,
1870-
[{ return Helper.isConstantLegalOrBeforeLegalizer(MRI.getType(${Zext}->getOperand(0).getReg())); }]),
1871-
(apply [{ Helper.replaceInstWithConstant(*${Zext}, 0); }])>;
1872-
1873-
def sext_undef: GICombineRule<
1874-
(defs root:$root),
1875-
(match (G_IMPLICIT_DEF $undef),
1876-
(G_SEXT $root, $undef):$Sext,
1877-
[{ return Helper.isConstantLegalOrBeforeLegalizer(MRI.getType(${Sext}->getOperand(0).getReg())); }]),
1878-
(apply [{ Helper.replaceInstWithConstant(*${Sext}, 0); }])>;
1879-
18801860
def cast_of_cast_combines: GICombineGroup<[
18811861
truncate_of_zext,
18821862
truncate_of_sext,
@@ -1902,10 +1882,7 @@ def cast_combines: GICombineGroup<[
19021882
narrow_binop_and,
19031883
narrow_binop_or,
19041884
narrow_binop_xor,
1905-
integer_of_truncate,
1906-
anyext_undef,
1907-
sext_undef,
1908-
zext_undef
1885+
integer_of_truncate
19091886
]>;
19101887

19111888
def canonicalize_icmp : GICombineRule<

‎llvm/test/CodeGen/AArch64/GlobalISel/combine-cast.mir

Lines changed: 0 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -217,55 +217,3 @@ body: |
217217
%large:_(<2 x s64>) = G_ANYEXT %bv(<2 x s32>)
218218
$q0 = COPY %large(<2 x s64>)
219219
$d0 = COPY %bv(<2 x s32>)
220-
...
221-
---
222-
name: test_combine_anyext_undef
223-
legalized: true
224-
body: |
225-
bb.1:
226-
; CHECK-PRE-LABEL: name: test_combine_anyext_undef
227-
; CHECK-PRE: %aext:_(s64) = G_IMPLICIT_DEF
228-
; CHECK-PRE-NEXT: $x0 = COPY %aext(s64)
229-
;
230-
; CHECK-POST-LABEL: name: test_combine_anyext_undef
231-
; CHECK-POST: %undef:_(s32) = G_IMPLICIT_DEF
232-
; CHECK-POST-NEXT: %aext:_(s64) = G_ANYEXT %undef(s32)
233-
; CHECK-POST-NEXT: $x0 = COPY %aext(s64)
234-
%undef:_(s32) = G_IMPLICIT_DEF
235-
%aext:_(s64) = G_ANYEXT %undef(s32)
236-
$x0 = COPY %aext(s64)
237-
...
238-
---
239-
name: test_combine_sext_undef
240-
legalized: true
241-
body: |
242-
bb.1:
243-
; CHECK-PRE-LABEL: name: test_combine_sext_undef
244-
; CHECK-PRE: %sext:_(s64) = G_CONSTANT i64 0
245-
; CHECK-PRE-NEXT: $x0 = COPY %sext(s64)
246-
;
247-
; CHECK-POST-LABEL: name: test_combine_sext_undef
248-
; CHECK-POST: %undef:_(s32) = G_IMPLICIT_DEF
249-
; CHECK-POST-NEXT: %sext:_(s64) = G_SEXT %undef(s32)
250-
; CHECK-POST-NEXT: $x0 = COPY %sext(s64)
251-
%undef:_(s32) = G_IMPLICIT_DEF
252-
%sext:_(s64) = G_SEXT %undef(s32)
253-
$x0 = COPY %sext(s64)
254-
...
255-
---
256-
name: test_combine_zext_undef
257-
legalized: true
258-
body: |
259-
bb.1:
260-
; CHECK-PRE-LABEL: name: test_combine_zext_undef
261-
; CHECK-PRE: %zext:_(s64) = G_CONSTANT i64 0
262-
; CHECK-PRE-NEXT: $x0 = COPY %zext(s64)
263-
;
264-
; CHECK-POST-LABEL: name: test_combine_zext_undef
265-
; CHECK-POST: %undef:_(s32) = G_IMPLICIT_DEF
266-
; CHECK-POST-NEXT: %zext:_(s64) = G_ZEXT %undef(s32)
267-
; CHECK-POST-NEXT: $x0 = COPY %zext(s64)
268-
%undef:_(s32) = G_IMPLICIT_DEF
269-
%zext:_(s64) = G_ZEXT %undef(s32)
270-
$x0 = COPY %zext(s64)
271-
...

‎llvm/test/CodeGen/AArch64/extract-vector-elt.ll

Lines changed: 11 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -8,10 +8,17 @@
88
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for extract_v4i32_vector_extract_const
99

1010
define i64 @extract_v2i64_undef_index(<2 x i64> %a, i32 %c) {
11-
; CHECK-LABEL: extract_v2i64_undef_index:
12-
; CHECK: // %bb.0: // %entry
13-
; CHECK-NEXT: fmov x0, d0
14-
; CHECK-NEXT: ret
11+
; CHECK-SD-LABEL: extract_v2i64_undef_index:
12+
; CHECK-SD: // %bb.0: // %entry
13+
; CHECK-SD-NEXT: fmov x0, d0
14+
; CHECK-SD-NEXT: ret
15+
;
16+
; CHECK-GI-LABEL: extract_v2i64_undef_index:
17+
; CHECK-GI: // %bb.0: // %entry
18+
; CHECK-GI-NEXT: str q0, [sp, #-16]!
19+
; CHECK-GI-NEXT: .cfi_def_cfa_offset 16
20+
; CHECK-GI-NEXT: ldr x0, [sp], #16
21+
; CHECK-GI-NEXT: ret
1522
entry:
1623
%d = extractelement <2 x i64> %a, i32 undef
1724
ret i64 %d

‎llvm/test/CodeGen/AMDGPU/GlobalISel/combine-amdgpu-cvt-f32-ubyte.mir

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -261,7 +261,8 @@ body: |
261261
; CHECK-LABEL: name: cvt_f32_ubyte0_zext_lshr_16
262262
; CHECK: liveins: $vgpr0
263263
; CHECK-NEXT: {{ $}}
264-
; CHECK-NEXT: %zext:_(s32) = G_CONSTANT i32 0
264+
; CHECK-NEXT: %shift:_(s16) = G_IMPLICIT_DEF
265+
; CHECK-NEXT: %zext:_(s32) = G_ZEXT %shift(s16)
265266
; CHECK-NEXT: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 %zext
266267
; CHECK-NEXT: $vgpr0 = COPY %result(s32)
267268
%arg:_(s32) = COPY $vgpr0
@@ -283,7 +284,8 @@ body: |
283284
; CHECK-LABEL: name: cvt_f32_ubyte0_zext_lshr_24
284285
; CHECK: liveins: $vgpr0
285286
; CHECK-NEXT: {{ $}}
286-
; CHECK-NEXT: %zext:_(s32) = G_CONSTANT i32 0
287+
; CHECK-NEXT: %shift:_(s16) = G_IMPLICIT_DEF
288+
; CHECK-NEXT: %zext:_(s32) = G_ZEXT %shift(s16)
287289
; CHECK-NEXT: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 %zext
288290
; CHECK-NEXT: $vgpr0 = COPY %result(s32)
289291
%arg:_(s32) = COPY $vgpr0

‎llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4074,12 +4074,14 @@ define amdgpu_kernel void @v_test_v2i16_x_add_undef_neg32(ptr addrspace(1) %out,
40744074
; VI-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
40754075
; VI-GISEL-NEXT: flat_load_dword v3, v[0:1]
40764076
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
4077-
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
40784077
; VI-GISEL-NEXT: v_add_u32_e32 v0, vcc, v0, v2
40794078
; VI-GISEL-NEXT: v_not_b32_e32 v2, 31
4079+
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
4080+
; VI-GISEL-NEXT: s_and_b32 s0, 0xffff, s0
40804081
; VI-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
40814082
; VI-GISEL-NEXT: s_waitcnt vmcnt(0)
40824083
; VI-GISEL-NEXT: v_add_u16_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
4084+
; VI-GISEL-NEXT: v_or_b32_e32 v2, s0, v2
40834085
; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
40844086
; VI-GISEL-NEXT: s_endpgm
40854087
;
@@ -4189,12 +4191,15 @@ define amdgpu_kernel void @v_test_v2i16_x_add_neg32_undef(ptr addrspace(1) %out,
41894191
; VI-GISEL-NEXT: v_add_u32_e32 v0, vcc, v0, v2
41904192
; VI-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
41914193
; VI-GISEL-NEXT: flat_load_dword v3, v[0:1]
4194+
; VI-GISEL-NEXT: s_and_b32 s2, 0xffff, s0
41924195
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
41934196
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
41944197
; VI-GISEL-NEXT: v_add_u32_e32 v0, vcc, v0, v2
4198+
; VI-GISEL-NEXT: s_lshl_b32 s0, s2, 16
41954199
; VI-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
41964200
; VI-GISEL-NEXT: s_waitcnt vmcnt(0)
41974201
; VI-GISEL-NEXT: v_add_u16_e32 v2, 0xffe0, v3
4202+
; VI-GISEL-NEXT: v_or_b32_e32 v2, s0, v2
41984203
; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
41994204
; VI-GISEL-NEXT: s_endpgm
42004205
;

0 commit comments

Comments
 (0)