[mlir][AMDGPU] "Added support for 64-bit operands in

ROCDL::DPPUpdateOp operation."

Author: stefankoncarevic

mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td

@@ -609,7 +609,7 @@ def ROCDL_DPPUpdateOp : ROCDL_IntrOp<"update.dpp", [], [0],
           builder.getInt32(op.getRowMask()),
           builder.getInt32(op.getBankMask()),
           builder.getInt1(op.getBoundCtrl())
-      }; 
+      };
       $res = createIntrinsicCall(builder,
         llvm::Intrinsic::amdgcn_update_dpp, args, {vdataType});
   }];

mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp

@@ -845,7 +845,9 @@ struct AMDGPUDPPLowering : public ConvertOpToLLVMPattern<DPPOp> {
     Value old = adaptor.getOld();
     Type srcType = src.getType();
     Type oldType = old.getType();
-    auto llvmI32Type = typeConverter->convertType(rewriter.getI32Type());
+    auto llvmType =
+        (srcType.getIntOrFloatBitWidth() <= 32 ? rewriter.getI32Type()
+                                               : rewriter.getI64Type());
     auto llvmSrcIntType = typeConverter->convertType(
         rewriter.getIntegerType(srcType.getIntOrFloatBitWidth()));
 
@@ -863,7 +865,7 @@ struct AMDGPUDPPLowering : public ConvertOpToLLVMPattern<DPPOp> {
         Value undefVec = rewriter.create<LLVM::UndefOp>(loc, llvmVecType);
         operand = rewriter.create<LLVM::InsertElementOp>(
             loc, undefVec, operand, createI32Constant(rewriter, loc, 0));
-        operand = rewriter.create<LLVM::BitcastOp>(loc, llvmI32Type, operand);
+        operand = rewriter.create<LLVM::BitcastOp>(loc, llvmType, operand);
       }
       return operand;
     };
@@ -951,7 +953,7 @@ struct AMDGPUDPPLowering : public ConvertOpToLLVMPattern<DPPOp> {
 
     // create a ROCDL_DPPMovOp instruction with the appropriate attributes
     auto dppMovOp = rewriter.create<ROCDL::DPPUpdateOp>(
-        loc, llvmI32Type, old, src, DppCtrl, rowMask, bankMask, boundCtrl);
+        loc, llvmType, old, src, DppCtrl, rowMask, bankMask, boundCtrl);
 
     Value result = dppMovOp.getRes();
     if (srcType.getIntOrFloatBitWidth() < 32) {

mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp

@@ -331,8 +331,8 @@ LogicalResult MFMAOp::verify() {
 //===----------------------------------------------------------------------===//
 LogicalResult DPPOp::verify() {
   Type srcType = getSrc().getType();
-  if (srcType.getIntOrFloatBitWidth() > 32) {
-    return emitOpError("integer and floating point types larger than 32 bits "
+  if (srcType.getIntOrFloatBitWidth() > 64) {
+    return emitOpError("integer and floating point types larger than 64 bits "
                        "are not supported");
   }
 

mlir/test/Conversion/AMDGPUToROCDL/dpp.mlir

@@ -18,14 +18,6 @@ func.func @quad_dpp(%arg0: i32, %arg1: i32) -> i32 {
     return %0 : i32
 }
 
-func.func @quad_perm_dpp(%arg0: i32, %arg1: i32) -> i32 {
-  // CHECK-LABEL: func @quad_perm_dpp
-  // CHECK: rocdl.update.dpp %arg0, %arg1 with 88, 15, 15, false : i32
-  // CHECK: return %0 : i32
-  %0 = amdgpu.dpp %arg0 %arg1 quad_perm ( [0,2,1,1] ) : i32
-    return %0 : i32
-}
-
 func.func @wave_shr_dpp(%arg0: i32, %arg1: i32) -> i32 {
   // CHECK-LABEL: func @wave_shr_dpp
   // CHECK: rocdl.update.dpp %arg0, %arg1 with 312, 10, 1, true : i32
@@ -34,14 +26,6 @@ func.func @wave_shr_dpp(%arg0: i32, %arg1: i32) -> i32 {
     return %0 : i32
 }
 
-func.func @row_bcast_dpp(%arg0: i32, %arg1: i32) -> i32 {
-  // CHECK-LABEL: func @row_bcast_dpp
-  // CHECK: rocdl.update.dpp %arg0, %arg1 with 323, 4, 1, false : i32
-  // CHECK: return %0 : i32
-  %0 = amdgpu.dpp %arg0 %arg1 row_bcast_31 { row_mask = 0x4 : i32, bank_mask = 0x1 : i32} : i32
-    return %0 : i32
-}
-
 func.func @row_bcast_dpp_f32(%arg0: f32, %arg1: f32) -> f32 {
   // CHECK-LABEL: func @row_bcast_dpp_f32
   // CHECK: llvm.bitcast %arg1 : f32 to i32
@@ -146,3 +130,22 @@ func.func @row_bcast_update_dpp_f16(%arg0: f16, %arg1: f16) -> f16 {
   %0 = amdgpu.dpp %arg0 %arg1 row_bcast_15 { bound_ctrl = true } : f16
     return %0 : f16
 }
+
+func.func @quad_perm_dpp(%arg0: i64, %arg1: i64) -> i64 {
+  // CHECK-LABEL: func @quad_perm_dpp
+  // CHECK: rocdl.update.dpp %arg0, %arg1 with 88, 15, 15, false : i64
+  // CHECK: return %0 : i64
+  %0 = amdgpu.dpp %arg0 %arg1 quad_perm ( [0,2,1,1] ) : i64
+    return %0 : i64
+}
+
+func.func @row_bcast_dpp(%arg0: f64, %arg1: f64) -> f64 {
+  // CHECK-LABEL: func @row_bcast_dpp
+  // CHECK: llvm.bitcast %arg1 : f64 to i64
+  // CHECK: llvm.bitcast %arg0 : f64 to i64
+  // CHECK: rocdl.update.dpp %1, %0 with 323, 4, 1, false : i64
+  // CHECK: llvm.bitcast %2 : i64 to f64
+  // CHECK: return %3 : f64
+  %0 = amdgpu.dpp %arg0 %arg1 row_bcast_31 { row_mask = 0x4 : i32, bank_mask = 0x1 : i32} : f64
+    return %0 : f64
+}